Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.
STA-driven Vt swapping: trade threshold-voltage flavors (iso-footprint) to cut leakage while holding timing, or to close setup.
Combinational logic equivalence check: two gate-level netlists in, an equivalence verdict (with counter-example) out.
STA-driven buffer insertion: split high-fanout / over-transition nets to fix slew and timing.
Headless GDS layout viewer: a GDS in, a layered SVG out — with optional violation overlay.
Liberty characterization — SPICE + PDK models to .lib (NLDM + CCS), parallel-SPICE orchestration.
RC parasitic extraction — routed layout to SPEF; a calibrated sky130 deck tracks OpenRCX.
Layout geometry kernel: GDSII read/write, polygon boolean ops, and hierarchy flatten.
Power analysis: per-instance leakage + dynamic power and the activity map that closes char -> power -> em-ir.
Static glitch/hazard analysis: a gate-level netlist + Liberty in, reconvergent-fanout hazards out.
Power-integrity sign-off — power-distribution-network IR-drop + electromigration against a budget.
Layout-vs-schematic: SPICE netlist comparison with clear divergence diagnostics.
Structural clock-domain-crossing (CDC) checker: netlist + clocks in, crossings out.
Steady-state on-chip thermal analysis + electro-thermal coupling — the thermal dual of vyges-em-ir
Gate sizing — STA-driven drive-strength resize to close setup or recover area.
The shared design-data foundation for the Vyges Loom EDA suite — parse-once/query-many readers (Verilog, Liberty, SDC, SPEF) + an in-memory design database.
Design-rule check: a GDS layout + a rule deck in, geometry violations out.
Add a description, image, and links to the vyges-loom topic page so that developers can more easily learn about it.
To associate your repository with the vyges-loom topic, visit your repo's landing page and select "manage topics."