vyges-layout

A memory-safe Rust layout geometry kernel: read/write GDSII, do polygon boolean operations, and flatten a cell hierarchy — the substrate the other layout-side tools ride on.

Vyges open EDA tools. Commercial-grade silicon capability, built on open standards and plain file formats — accessible to everyone. vyges-layout is the geometry kernel under LVS extraction, DRC, fill, and the chip viewer.

Docs: docs.vyges.com — this engine's chapter and the cross-engine integration guide. In-repo: docs/engines-integration.md, docs/kernel-notes.md. Integrating and need help? → https://vyges.com/contact.

Why this exists

Everything on the layout side is geometry: LVS device extraction (GDS → devices + nets), DRC (width/spacing), metal fill, and viewing a die — they all need to read GDSII, do boolean operations on shapes, and flatten hierarchy. The open peers (KLayout's database, gdstk) are excellent but C++; vyges-layout is the clean-room, memory-safe Rust kernel, so the Vyges layout tools (and the chip viewer) build on a single, auditable, std-only base — and it's the dependency that unblocks vyges-lvs native extraction.

Use it

cargo build --release            # std-only, no external deps

vyges-layout info    block.gds                 # cells, layers, areas, bbox
vyges-layout info    block.gds --json
vyges-layout boolean block.gds --top top --op and --a 67/20 --b 68/20 --out 100/0 -o and.gds
vyges-layout flatten block.gds --top top -o flat.gds
vyges-layout demo                              # built-in, no files
# `L/D` is layer/datatype; boolean ops: and · or · not (A−B) · xor
# common flags: -o FILE · --json · -q/--quiet · -v/--verbose · -h/--help · -V/--version

A runnable example is generated by cargo run --example gen (committed as examples/two_box.gds): two overlapping metal boxes (for boolean) + two placements of a leaf cell (for flatten).

Domain coverage — digital and analog / mixed-signal

The kernel is pure geometry: layers, datatypes, and polygons. Nothing in read/write, boolean, or flatten knows or cares whether a shape is a standard cell or an analog device — so vyges-layout applies to digital, analog, and mixed-signal layouts identically.

• Digital: examples/two_box.gds — overlapping metal boxes + a placed leaf cell.
• Analog: examples/analog/ — a non-standard-cell block (a guard ring, a MIM capacitor, and a poly resistor snake). tests/analog.rs proves (a) the GDS write→read round-trips every shape and vertex exactly, and (b) a boolean across two layers is correct: MIM top-plate AND bottom-plate = the exact cap-overlap rectangle, and OR of the two guard-ring halves reunites the full rectilinear ring.

cargo run --example gen_analog   # (re)writes examples/analog/analog.gds
cargo test --test analog         # round-trip + cross-layer boolean on the analog block

The v0 boolean is Manhattan (rectilinear, exact on integer DBU) — that bound is about the geometry (general-angle clipping is the depth pass), not about the design domain; the analog shapes above are rectilinear and handled exactly.

What it does (v0)

• GDSII read/write — round-trips a library (BOUNDARY/PATH/SREF/AREF/BOX; the GDS real format for units). This replaces the vendored JS GDS parser in the chip viewer.
• info — cells, per-cell element counts, layers present, per-layer boundary count and area, in text or JSON.
• boolean — AND / OR / NOT / XOR between two layers via a vertical scanline on rectilinear polygons (rectangles, L-shapes, holey/overlapping Manhattan shapes; integer coordinates → exact), output to a layer.
• flatten — expand SREF/AREF hierarchy into one cell (reflect → mag → rotate → translate, composed; AREF arrays expanded; cycles guarded).

Honest bounds (depth reserved). v0 boolean is Manhattan — it handles any rectilinear polygon exactly, but the result is returned as a set of rectangles tiling the region (contour-tracing into merged polygons is depth), and general-angle geometry (a diagonal edge) is bbox-approximated and counted (never silently dropped). General clipping (Vatti) is the depth pass. Arbitrary reference angles round to integer DBU. Reserved: OASIS, sizing + region queries (DRC width/spacing), and net tracing for device extraction (the piece vyges-lvs Phase 2 consumes).

License

Apache-2.0, clean-room (no third-party EDA database). The peers (KLayout-db, gdstk) are libraries, not products; this is the Rust one.

Current state (v0)

GDSII read/write, info, Manhattan boolean (and/or/not/xor), and hierarchy flatten; text + JSON; runnable example. Pure std, unit + example tested offline, no subprocess.