GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
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Jan 23, 2024 - Verilog
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rtl-gds
Here are 7 public repositories matching this topic...
ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.
rtl verilog cadence modus asic-design cadence-incisive cadence-conformal innovus cadence-xcelium rtl-gds genus-synthesis
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Nov 10, 2025 - Verilog
The road to tapeout is real. Welcome to my assignment hub! Physical Design w/ASICs Aug-Dec'23
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Nov 26, 2023 - C
This Repo is to demonstrate RTL to GDSII design implementation
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Oct 6, 2023 - Verilog
A synthesizable SPI Master–Slave full-duplex communication module implemented in Verilog HDL. This repository covers the complete RTL-to-GDS flow using Cadence tools, including RTL design, verification, synthesis, place-and-route, and timing analysis.
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Dec 20, 2025 - Verilog
End-to-end Microwatt-based SoC with AXI-Lite, Wishbone, and APB buses, fully verified using Cocotb and taken from RTL to GDSII on Sky130 using OpenLane.
verification openpower soc vlsi wishbone axi apb cocotb asic-verification openlane sky130 microwatt rtl-gds chipfoundry
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Jan 5, 2026 - Verilog
This repository contains the report of the Week 2 task for VSD RV SoC Tapeout Program
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Oct 4, 2025
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