Hardware Engineer at Ilensys Technologies | Transitioning into VLSI Design and Verification | Passionate about Semiconductor Innovation
- Hyderabad, India
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18:21
(UTC +05:30) - in/rohith-veer-007
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NASSCOM_SEMICONDUCTOR_WORKSHOP-July-4-to-13-2025
NASSCOM_SEMICONDUCTOR_WORKSHOP-July-4-to-13-2025 Public -
SILICLUSTER_UART_TX_and_UART_RX_2025
SILICLUSTER_UART_TX_and_UART_RX_2025 PublicVerilog implementation of UART Transmitter and Receiver modules designed for Silicluster 2025 using SkyWater 130 nm PDK. Includes RTL design, functional testbenches, OpenLane-generated GDS layouts,…
Verilog
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MICROWATT_AXI_WISHBONE_APB_SOC_2025
MICROWATT_AXI_WISHBONE_APB_SOC_2025 PublicEnd-to-end Microwatt-based SoC with AXI-Lite, Wishbone, and APB buses, fully verified using Cocotb and taken from RTL to GDSII on Sky130 using OpenLane.
Verilog
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