Neural Network models for automating design parameters of CS amplifier. Includes automated SPICE data generation and model validation in Python and MATLAB.
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Updated
May 15, 2026 - Jupyter Notebook
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eda-automation
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An automated RTL-to-Synthesis EDA tool wrapper written in Tcl. Automates multi-module hierarchy checks, SDC constraint generation, Yosys synthesis mapping, and OpenTimer static timing analysis (STA) for the openMSP430 core.
verilog vlsi logic-synthesis yosys tcl-scripts static-timing-analysis opentimer openmsp430 eda-automation
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Updated
May 26, 2026 - Verilog
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