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rajjoshi2009/README.md

💫 About Me:

I am a B.Tech Electronics & Communication Engineering undergraduate with a strong interest in the VLSI and Semiconductor Industry.
My primary focus is on Digital Design (RTL using Verilog) and ASIC Physical Design.
I have hands-on exposure to RTL-to-GDSII flow using industry-aligned open-source and academic EDA tools and I am actively preparing for core VLSI roles and internships.

🌐 Socials

LinkedIn GitHub Portfolio

💻 Tech Stack:

🔹 RTL & Digital Design

Verilog Digital Design

🔹 ASIC Physical Design & EDA Tools

OpenLane KLayout VSD Flow

🔹 Cadence Tools (Academic Exposure)

Cadence Cadence Genus Cadence Innovus

🔹 Programming & Simulation

C MATLAB Linux

🔹 Embedded Systems

Arduino

🧪 Projects:

🔸 32-bit Adder Design using Verilog HDL

  • Designed a synthesizable 32-bit adder at RTL level
  • Verified functionality using testbenches and waveform analysis
  • Understood combinational logic design and RTL simulation flow
    Tools: Verilog HDL, GTKWave, OpenLane (introductory flow)

🔸 Sign Language to Speech Converter

  • Developed an embedded system to convert hand gestures into speech output
  • Worked on sensor interfacing and microcontroller-based signal processing
    Tools: Arduino, Embedded C

📚 Currently Learning / Upskilling:

  • Advanced Verilog & RTL Coding Techniques
  • ASIC Physical Design Flow (Floorplanning, Placement, Routing)
  • Static Timing Analysis (STA – basics)
  • Semiconductor Design Flow (Frontend to Backend)
  • Interview-oriented Digital Electronics & VLSI concepts

🎯 Career Objective:

To secure an entry-level role or internship in the VLSI / Semiconductor industry, where I can contribute to RTL design or ASIC physical design teams while continuously improving my technical expertise.

📊 GitHub Stats:



Popular repositories Loading

  1. rajjoshi2009 rajjoshi2009 Public

    Config files for my GitHub profile.

  2. leetcode_solutions leetcode_solutions Public

    I am solving leetcode problems to starting my DSA Preparation.

  3. assignments assignments Public

    Forked from 100xdevs-cohort-2/assignments

    JavaScript

  4. rtl-verilog rtl-verilog Public

    Verilog HDL practice repository with chapter-wise RTL implementations developed during FPGA laboratory work.

    Verilog

  5. hdlbits-solutions hdlbits-solutions Public

    Solutions of Problem Set on the hdlbits plateform. Its like Leetcode for ECE Engineer.

    Verilog

  6. RTL-to-GDS-16bit-Counter RTL-to-GDS-16bit-Counter Public

    Forked from Rachith-H/RTL-to-GDS-16bit-Counter

    Complete RTL-to-GDSII implementation of a synchronous counter using OpenLane and Sky130 PDK. This project demonstrates the full ASIC digital flow from Verilog RTL through synthesis, floorplanning, …

    Verilog