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Merged
titzer merged 4 commits into from
Jan 21, 2026
Merged

Refactor V3Offsets creation #552

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2776ed7
[misc] Cleaned up `V3Offsets` allocation in interpreter
linxuanm Jan 20, 2026
ec2e8ee
[misc] Cleaned up `V3Offsets` allocation in masm
linxuanm Jan 20, 2026
7c5fec0
[misc] Removed duplicate `offsets` field in masm
linxuanm Jan 20, 2026
a1980bb
[misc] Moved the only `V3Offsets` instantiation to `X86_64Target`
linxuanm Jan 20, 2026
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3 changes: 1 addition & 2 deletions src/engine/compiler/MacroAssembler.v3
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Original file line number Diff line number Diff line change
Expand Up @@ -25,15 +25,14 @@ class MacroAssembler(valuerep: Tagging, regConfig: RegConfig) {
var source_loc: int = -1; // current source location, if any
var newTrapLabel: TrapReason -> MasmLabel;
var embeddedRefOffsets: Vector<int>;
private var offsets: V3Offsets;
var offsets = Target.getOffsets();

new() {
unimplemented = fatalUnimplemented;
newTrapLabel = makeSharedTrapLabel;
}

def getOffsets() -> V3Offsets {
if (offsets == null) offsets = V3Offsets.new();
return offsets;
}
def curCodeBytes() -> u64 {
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5 changes: 0 additions & 5 deletions src/engine/compiler/SinglePassCompiler.v3
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Expand Up @@ -1381,7 +1381,6 @@ class SinglePassCompiler(xenv: SpcExecEnv, masm: MacroAssembler, regAlloc: RegAl
}
}

var offsets = V3Offsets.new();
var stub_resume = masm.newLabel(it.pc), end = masm.newLabel(it.pc);
var cont_decl = ContDecl.!(module.heaptypes[cont_id]);
if (checkForConstNull(state.peek())) return;
Expand Down Expand Up @@ -1435,7 +1434,6 @@ class SinglePassCompiler(xenv: SpcExecEnv, masm: MacroAssembler, regAlloc: RegAl
masm.bindLabel(end);
}
def visit_SUSPEND(tag_index: u31) {
var offsets = V3Offsets.new();
var stub_suspend = masm.newLabel(it.pc), end = masm.newLabel(it.pc);

state.emitSaveAll(resolver, SpillMode.SAVE_AND_FREE_REGS);
Expand Down Expand Up @@ -1476,7 +1474,6 @@ class SinglePassCompiler(xenv: SpcExecEnv, masm: MacroAssembler, regAlloc: RegAl
masm.bindLabel(end);
}
def visit_SWITCH(target_cont_idx: u31, tag_index: u31) {
var offsets = V3Offsets.new();
var stub_switch = masm.newLabel(it.pc), end = masm.newLabel(it.pc);

state.emitSaveAll(resolver, SpillMode.SAVE_AND_FREE_REGS);
Expand Down Expand Up @@ -1534,7 +1531,6 @@ class SinglePassCompiler(xenv: SpcExecEnv, masm: MacroAssembler, regAlloc: RegAl
}
}

var offsets = V3Offsets.new();
var stub_resume = masm.newLabel(it.pc), end = masm.newLabel(it.pc);
var cont_decl = ContDecl.!(module.heaptypes[cont_id]);
var tag = module.tags[tag_id];
Expand Down Expand Up @@ -1611,7 +1607,6 @@ class SinglePassCompiler(xenv: SpcExecEnv, masm: MacroAssembler, regAlloc: RegAl
}
}

var offsets = V3Offsets.new();
var stub_resume = masm.newLabel(it.pc), end = masm.newLabel(it.pc);
var cont_decl = ContDecl.!(module.heaptypes[cont_id]);
if (checkForConstNull(state.peek())) return;
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2 changes: 1 addition & 1 deletion src/engine/x86-64/X86_64Interpreter.v3
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Expand Up @@ -249,7 +249,7 @@ class X86_64InterpreterGen(ic: X86_64InterpreterCode, w: DataWriter) {
def asm = masm.asm;
def xenv: IntExecEnv = X86_64MasmRegs.INT_EXEC_ENV;

def offsets = V3Offsets.new();
def offsets = masm.getOffsets();
def valuerep = Target.tagging;
def initialSize = w.data.length;

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5 changes: 0 additions & 5 deletions src/engine/x86-64/X86_64MacroAssembler.v3
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Expand Up @@ -20,7 +20,6 @@ class X86_64MacroAssembler extends MacroAssembler {
def asm = X86_64Assemblers.create64(w);
var scratch: X86_64Gpr;
var jump_tables: Vector<(int, Array<X86_64Label>)>;
var offsets: V3Offsets;
var trap_stubs: X86_64SpcTrapsStub;

new(w, regConfig: RegConfig) super(Target.tagging, regConfig) {
Expand Down Expand Up @@ -1550,10 +1549,6 @@ class X86_64MacroAssembler extends MacroAssembler {
def absPointer(ptr: Pointer) -> X86_64Addr {
return X86_64Addr.new(null, null, 1, int.view(u32.!(ptr - Pointer.NULL)));
}
def getOffsets() -> V3Offsets {
if (offsets == null) offsets = V3Offsets.new();
return offsets;
}

def emit_set_stack_state(stk: Reg, state: StackState) {
emit_mov_m_i(MasmAddr(stk, offsets.X86_64Stack_state), state.tag);
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5 changes: 2 additions & 3 deletions src/engine/x86-64/X86_64SinglePassCompiler.v3
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Expand Up @@ -998,7 +998,7 @@ class X86_64SinglePassCompiler extends SinglePassCompiler {
mmasm.load_v128_mask(r_xmm0, mmasm.mask_i16x8_splat_0x0001, t);
asm.pmaddwd_s_s(r_xmm0, r_xmm1);
asm.paddd_s_s(r_xmm0, r_xmm2);

state.push(a.kindFlagsMatching(ValueKind.V128, IN_REG), a.reg, 0);
}

Expand Down Expand Up @@ -1406,9 +1406,8 @@ def genTierUpCompileStub(ic: X86_64InterpreterCode, w: DataWriter) {
var func_arg = G(regs.func_arg);
// Decrement execution counter by 1 and compile if <= 0
var scratch = X86_64MasmRegs.R15; // XXX: regs.func_arg == scratch!
var offsets = V3Offsets.new();
masm.emit_v3_WasmFunction_decl_r_r(scratch, regs.func_arg);
asm.q.sub_m_i(G(scratch).plus(offsets.FuncDecl_tierup_trigger), FastIntTuning.entryTierUpDecrement);
asm.q.sub_m_i(G(scratch).plus(masm.getOffsets().FuncDecl_tierup_trigger), FastIntTuning.entryTierUpDecrement);
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@titzer titzer Jan 20, 2026

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There is still an offsets field, correct? I think we should make the SPC uniformly use its own offsets field then.

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@linxuanm linxuanm Jan 20, 2026

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There isn't an offsets field in SPC anymore as I intended for the MacroAssembler to store/cache it. Should I also cache it in SPC?

var interpreter_entry = X86_64Label.new();
interpreter_entry.pos = ic.header.intSpcEntryOffset;
asm.jc_rel_near(C.A, interpreter_entry); // jump to interpreter if >= 0
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12 changes: 9 additions & 3 deletions src/engine/x86-64/X86_64Target.v3
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Expand Up @@ -13,13 +13,15 @@ component Target {

def limit_memory_size = 0x1_0000uL * 0x1_0000uL;
def limit_memory_size_64 = 0x4_0000uL * 0x1_0000uL;

def newMemory = NativeWasmMemory.new;
def forceGC = RiGc.forceGC;
def newWasmStack = X86_64StackManager.getFreshStack;
def recycleWasmStack = X86_64StackManager.recycleStack;
def tagging = Tagging.new(!FeatureDisable.valueTags, !FeatureDisable.simd);

private var offsets: V3Offsets;

new() {
if (!SpcTuning.disable) {
ExecuteOptions.registerMode("spc", X86_64SpcAotStrategy.new(false), "pre-compile modules with SPC, no fallback");
Expand All @@ -33,6 +35,11 @@ component Target {
Instrumentation.probes.onDisable = X86_64Interpreter.onProbeDisable;
}

def getOffsets() -> V3Offsets {
if (offsets == null) offsets = V3Offsets.new();
return offsets;
}

def getTestTiers() -> List<(string, ExecutionStrategy)> {
var spc_mode = ("jit:", X86_64SpcAotStrategy.new(true));
var int_mode = ("int:", X86_64InterpreterOnlyStrategy.new());
Expand Down Expand Up @@ -374,12 +381,11 @@ class X86_64DynamicStrategy extends X86_64SpcStrategy {
installStubForModule(module, X86_64Spc.setTierUpFor);
disableLazyNameDecodingDuringGC(module);
if (Debug.runtime) {
var offsets = V3Offsets.new();
for (i < module.functions.length) {
var func = module.functions[i];
Trace.OUT.put2(
"Compiled function #%d: addr(target_code) = 0x%x", i,
Pointer.atObject(func) + offsets.FuncDecl_target_code - Pointer.NULL
Pointer.atObject(func) + Target.getOffsets().FuncDecl_target_code - Pointer.NULL
).ln();
}
}
Expand Down