GitHub - papaonlegs/Washing-Machine-Controller: VHDL implementation of a washing machine controller

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
Controller_1.vhd		Controller_1.vhd
Controller_1_tb.vhd		Controller_1_tb.vhd
Controller_2.vhd		Controller_2.vhd
Controller_3.vhd		Controller_3.vhd
README		README
alu.vhd		alu.vhd
and_gate.vhd		and_gate.vhd
d_flipflop.vhd		d_flipflop.vhd
datapath.vhd		datapath.vhd
eight_n_bit_register_file.vhd		eight_n_bit_register_file.vhd
four_bit_LAC.vhd		four_bit_LAC.vhd
four_bit_LAC_adder.vhd		four_bit_LAC_adder.vhd
four_bit_adder_subtractor.vhd		four_bit_adder_subtractor.vhd
four_bit_arithmetic_unit.vhd		four_bit_arithmetic_unit.vhd
four_bit_shifter.vhd		four_bit_shifter.vhd
four_input_multiplexer.vhd		four_input_multiplexer.vhd
full_adder.vhd		full_adder.vhd
function_decode_logic.vhd		function_decode_logic.vhd
function_decode_logic_tb.vhd		function_decode_logic_tb.vhd
half_adder.vhd		half_adder.vhd
logic_slice.vhd		logic_slice.vhd
mcd1.vhd		mcd1.vhd
mcd1_tb.vhd		mcd1_tb.vhd
mcd2.vhd		mcd2.vhd
mcd3.vhd		mcd3.vhd
n_bit_2_input_multiplexer.vhd		n_bit_2_input_multiplexer.vhd
n_bit_adder.vhd		n_bit_adder.vhd
n_bit_incrementer.vhd		n_bit_incrementer.vhd
n_bit_load_hold_tristate_output_register.vhd		n_bit_load_hold_tristate_output_register.vhd
n_bit_logic_unit.vhd		n_bit_logic_unit.vhd
n_bit_register.vhd		n_bit_register.vhd
n_bit_register_with_load_hold_control.vhd		n_bit_register_with_load_hold_control.vhd
n_bit_shifter_rotator_unit.vhd		n_bit_shifter_rotator_unit.vhd
n_bit_synchronous_counter_with_parallel_load.vhd		n_bit_synchronous_counter_with_parallel_load.vhd
n_bit_synchronous_counter_with_parallel_load_tb.vhd		n_bit_synchronous_counter_with_parallel_load_tb.vhd
n_bit_tri_state_buffer.vhd		n_bit_tri_state_buffer.vhd
n_bit_xor_control.vhd		n_bit_xor_control.vhd
not_gate.vhd		not_gate.vhd
or_gate.vhd		or_gate.vhd
output_rom_1.vhd		output_rom_1.vhd
output_rom_1_tb.vhd		output_rom_1_tb.vhd
output_rom_2.vhd		output_rom_2.vhd
output_rom_3.vhd		output_rom_3.vhd
rand		rand
rfc.vhd		rfc.vhd
rfc_register.vhd		rfc_register.vhd
shift_control_logic.vhd		shift_control_logic.vhd
status_logic.vhd		status_logic.vhd
status_logic_tb.vhd		status_logic_tb.vhd
three_to_eight_decoder.vhd		three_to_eight_decoder.vhd
tri_buff.vhd		tri_buff.vhd
two_input_multiplexer.vhd		two_input_multiplexer.vhd
xor_gate.vhd		xor_gate.vhd

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<H1> WASHING MACHINE CONTROLLER <H1>

Testbenches included for major components so you can test using Xilinx or similar.

Note : You're going to need at least 4 input buttons (exluding clock) for this to work on your FPGA or other device.

Controller_1 is a good place to start :)