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zafeerzafar/README.md

Muhammad Zafeer Zafar

Embedded Systems Engineer specializing in FPGA-based systems, real-time firmware, and Edge AI.

Currently working on:

  • FPGA-based Data Acquisition Systems (DAQ)
  • Xilinx ZYNQ-7000 SoC platforms
  • Bare-metal ARM Cortex-A9 firmware
  • Embedded ML on STM32 and ESP32

Featured Projects

🚀 FPGA Data Acquisition System

  • High-speed ADC acquisition using ZYNQ-7000
  • Real-time ARM-FPGA data pipeline

🧠 Edge AI Object Detection

  • YOLOv8 deployment on ESP32-CAM
  • Low-power embedded inference

⚙️ RISC-V Processor Core

  • 3-stage pipelined processor in SystemVerilog
  • Verified and deployed on FPGA hardware

Tech Stack

C • SystemVerilog • FPGA • STM32 • ESP32 • FreeRTOS • Vivado • Vitis • PyTorch • TensorFlow Lite • EasyEDA • KiCad

Connect

LinkedIn

Upwork

Email

Popular repositories Loading

  1. PoE-Human-Presence-Sensor-Board PoE-Human-Presence-Sensor-Board Public

    4-layer ESP32-S3 PoE board for mmWave human presence detection. Supports LD2410B/C, LD2420, LD2450, LD2412. Galvanic isolation between PoE and other components. Impedance-controlled Ethernet & USB …

    1

  2. zafeerzafar zafeerzafar Public

  3. RISC-V-Based-3-Stage-Pipelined-CPU-Core RISC-V-Based-3-Stage-Pipelined-CPU-Core Public

    A 32-bit RISC-V processor implemented in SystemVerilog featuring a custom 3-stage pipeline architecture, support for major RV32I instruction formats, simulation-based verification, and successful d…

    SystemVerilog