GitHub - xdesigns/4way-cache: Verilog cache implementation of 4-way FIFO 16k Cache

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
.gitattributes		.gitattributes
.gitignore		.gitignore
Readme.txt		Readme.txt
blockMux_256x1.v		blockMux_256x1.v
cache.v		cache.v
cacheAuxArray.v		cacheAuxArray.v
cacheBlock.v		cacheBlock.v
cacheByte.v		cacheByte.v
cacheMux_2x1_4bit.v		cacheMux_2x1_4bit.v
cacheMux_4x1_8bit.v		cacheMux_4x1_8bit.v
cacheTag.v		cacheTag.v
cacheWay.v		cacheWay.v
comparator_11bit.v		comparator_11bit.v
counter.v		counter.v
dFlipFlop.v		dFlipFlop.v
decoder_2x4.v		decoder_2x4.v
decoder_4x16.v		decoder_4x16.v
decoder_8x256.v		decoder_8x256.v
fifo_replacement.v		fifo_replacement.v
mux_16x1.v		mux_16x1.v
mux_2x1_2bit.v		mux_2x1_2bit.v
priorityEncoder_4x2.v		priorityEncoder_4x2.v
refBits.v		refBits.v
refMux_256x1_8bit.v		refMux_256x1_8bit.v
replacementWay.v		replacementWay.v
tagMux_256x1.v		tagMux_256x1.v
upCounter_4bit.v		upCounter_4bit.v

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16K 4-way associate FIFO cache design using write-through write no-allocate policy
By Nijith Jacob (nijith89@gmail.com)

This project contains all the necessary verilog files with cache.v as the top level module.


For any questions, please contact me.

Enjoy!