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Add support for Sverio Paperboard v1 board definition#438

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Pajenicko wants to merge 7 commits into
vroland:mainfrom
Pajenicko:feature/add-sverio-paperboard-v1-support
Open

Add support for Sverio Paperboard v1 board definition#438
Pajenicko wants to merge 7 commits into
vroland:mainfrom
Pajenicko:feature/add-sverio-paperboard-v1-support

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@Pajenicko

@Pajenicko Pajenicko commented Aug 9, 2025

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Adds a board definition for the Sverio Paperboard v1 (ESP32-S3 based EPDIY-compatible driver board by Pajenicko).

  • src/board/epd_board_sverio_paperboard_v1.c — board definition (sverio_paperboard_v1), TPS65185 + PCA9555 based, 16-bit LCD bus on the ESP32-S3
  • Registered in CMakeLists.txt and src/epd_board.h

Tested with the dragon example on real hardware (ED097TC2, VCOM -1.56 V).

The board design files (schematic/gerbers) are not published yet — a link will be added here once they are released as open source.

@martinberlin

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Hello I'm on holidays till the end of August. When I come back will send you my address via a PM, let's do something:

  • You send me one of my boards. I send you back the package with one of my custom v7 boards.

Then I can also test the board. About the naming:

"src/board/sverio_paperboard_v1.c" --> Please follow the epd_board_ prefix.
epd_board_sverio_paperboard_v1.c would be fine. You can also exclude the brand and make it smaller if you want. The important thing is that your users know that paperboard is your board and it will be referenced in your examples and firmware anyways.

@martinberlin martinberlin self-assigned this Aug 17, 2025
@martinberlin

martinberlin commented Dec 13, 2025

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Hello @Pajenicko
tried this with the board you sent me and the dragon example and I'm getting:

I (132159) epdiy: Using optimized vector implementation on the ESP32-S3, only 1k of 65536 LUT in use!
I (132549) epdiy: diff: 33ms, draw: 380ms, buffer update: 16ms, total: 429ms
I (133659) epdiy: Using optimized vector implementation on the ESP32-S3, only 1k of 65536 LUT in use!
I (134049) epdiy: diff: 33ms, draw: 380ms, buffer update: 16ms, total: 429ms
E (145159) epdiy: Power Good Status: 0xFA
E (145159) epdiy: VB_PG: 1
E (145159) epdiy: VDDH_PG: 1
E (145159) epdiy: VN_PG: 1
E (145159) epdiy: VPOS_PG: 1
E (145159) epdiy: VEE_PG: 1
E (145169) epdiy: VNEG_PG: 1

using this initialisation on this PR branch on your repository:

void idf_setup() {
    epd_init(&sverio_paperboard_v1, &ED097TC2, EPD_LUT_64K);
    epd_set_vcom(1560);
    hl = epd_hl_init(EPD_BUILTIN_WAVEFORM);
}

Voltage grid wont go up after this messages. Is the board you sent me correct with this PR pinout setting?

@martinberlin martinberlin added the Waiting for feedback If it's in this state more than 2 months without feedback then the Issue/MR will be closed label Dec 13, 2025
@martinberlin

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So @Pajenicko what we do with this? You want to send me an additional board or we leave it as is and merge it?

@Pajenicko

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Hello, damn, I forgot .. sure, will send you new board on tuesday, right after easter!

@martinberlin

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If you can please pull again this branch and run a:
clang-format ./src/board/sverio_paperboard_v1.c

To fix automatically the C lang formatting. Then just push the changes so the CI checks will pass

@Pajenicko

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Hi, quick update: a new pre-flashed board has been shipped to you today, so you should receive it soon. Hopefully this one boots up correctly and you'll be able to verify the pinout against the PR.

Also pushed a follow-up commit addressing your feedback:

  • Renamed the file to epd_board_sverio_paperboard_v1.c (added the epd_board_ prefix)
  • Ran clang-format so CI should pass now

@martinberlin

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Please open a new PR since main branch changed already since you added this. Then you can add this changes fresh over the last changes.
Then I will test again but your board is now working. Please add also a link to your open source board design files.

@martinberlin

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Hey @Pajenicko can you please try merging main back in this branch and pushing changes?
Then we could run the tests and try it again. Since your updates didn’t changed any of the core files it should work.

@martinberlin

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Dear @Pajenicko please take action on this no longer than 15 or as latest 20 June. I asked you before if you are willing to merge main back here or you prefer to re-make the PR on the latest updates.
Just take action so we finish with this one. I'm not a big fan of having PRs open over a lifetime for obvious reasons

Pajenicko added 3 commits June 7, 2026 07:00
Adapt to upstream changes from the merge of main:
- epd_board_init() takes an EpdInitConfig parameter (vroland#452)
- legacy i2c driver replaced by epd_board_i2c helper (vroland#475)
- pca9555/tps65185 calls now use i2c_master device handles
printPowerGoodStatus() is also called on successful power-up, so log at
INFO level instead of ERROR. Make it static to avoid leaking a global
symbol.
@Pajenicko

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@martinberlin done:

  • Merged current main back into this branch (no conflicts).
  • Migrated the board file to the new APIs that landed in main since this PR was opened: the new EpdInitConfig parameter of init (#451 Implement UPSEQ #452)
    and the new i2c_master-based driver via the epd_board_i2c helper (Migrate epdiy board I2C init to the new ESP-IDF driver #475) - without this the branch wouldn't compile against current
    main.
  • Changed the power-good status logging to ESP_LOGI (it was logged with ESP_LOGE even on successful power-up, which made the log you
    posted earlier look like a failure - 0xFA actually means all rails are good).
  • Verified on real hardware after the merge: dragon example on the Paperboard v1 + ED097TC2, power rails come up fine and the refresh
    timings match what you measured (diff: 32ms, draw: 381ms, total: 428ms). Builds checked for both esp32s3 and esp32 targets with IDF
    v5.4.4.
  • The board design files are now published as open source (CC-BY-SA-4.0, derived from EPDIY v7):
    https://github.com/Pajenicko/Paperboard-hardware/tree/main/paperboard-epdiy - KiCad project, schematic PDF, 3D models and fabrication
    outputs.

@martinberlin

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Small fix here just to pass clang validation, just install it on your machine so it's available in command line. Then just do:

clang-format -i /path/to/file.c

OR:
2. Integrate with VS Code (Recommended)
To stop fighting formatting errors manually, configure VS Code to use the exact ESP-Clang binary you provided.
Install the official Clang-Format extension by Xaver Hellauer.
Open your project's .vscode/settings.json file.
Add the following configuration, pointing directly to your ESP-IDF clang-format executable:
JSON
{
"editor.formatOnSave": true,
"[{cpp,c}]": {
"editor.defaultFormatter": "xaver.clang-format"
},
"clang-format.executable": "/opt/esp/tools/esp-clang/esp-18.1.2_20240912/esp-clang/bin/clang-format"
}
💡 Tip: Setting "editor.formatOnSave": true ensures that every time you hit save, your code is instantly aligned with the ESP-IDF style guidelines.

@martinberlin

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@vroland this is now ready. About the board maybe is possible to make an "external board" section of boards that are not epdiy but built in the same fashion and license?

https://github.com/Pajenicko/Paperboard-hardware/tree/main/paperboard-epdiy - KiCad project, schematic PDF, 3D models and fabrication

@martinberlin martinberlin requested a review from vroland June 7, 2026 19:49
@martinberlin martinberlin added done Implemented and tested and removed Waiting for feedback If it's in this state more than 2 months without feedback then the Issue/MR will be closed labels Jun 7, 2026
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