VLSI lab - PoliTO
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Mage-and-Rogue
Mage-and-Rogue PublicTemplate-based CGRA allowing for generating GeMM CGRA with internal memory (Mage) and DMA-coupled streaming CGRA (Rogue)
Python 8
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- Mage-and-Rogue Public
Template-based CGRA allowing for generating GeMM CGRA with internal memory (Mage) and DMA-coupled streaming CGRA (Rogue)
vlsi-lab/Mage-and-Rogue’s past year of commit activity - CryptoLib Public Forked from nasa/CryptoLib
Provide a software-only solution using the CCSDS Space Data Link Security Protocol - Extended Procedures (SDLS-EP) to secure communications between a spacecraft running the core Flight System (cFS) and a ground station.
vlsi-lab/CryptoLib’s past year of commit activity - riscv-Xilinx-SoCs-toolchain Public
RISC-V GCC Toolchain for X-HEEP (OpenHW Core-V) pre-build for ARM Hosts
vlsi-lab/riscv-Xilinx-SoCs-toolchain’s past year of commit activity - onnx-codegen Public
vlsi-lab/onnx-codegen’s past year of commit activity - HORCRUX Public
vlsi-lab/HORCRUX’s past year of commit activity - VLSPQC Public
vlsi-lab/VLSPQC’s past year of commit activity - rv_profile Public Forked from LucasKl/riscv-function-profiling
Visualize what your RISC-V core is executing
vlsi-lab/rv_profile’s past year of commit activity - cva6 Public Forked from openhwgroup/cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
vlsi-lab/cva6’s past year of commit activity - astral Public Forked from pulp-platform/astral
A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
vlsi-lab/astral’s past year of commit activity
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