AArch64 EL1 4KB paging#408
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1.add set_formal_linearmap 2.add flush_tlb_all() 3.clear pagetable memory after get a page from heap 4.Linearmap based on paging works fine, but needs to be streamlined 5.rename KERNEL_TCR_TSZ -> TCR_TSZ 6.Increase the heap_size to 32MB, accommodate the 4KB granularity paging mechanism. 7.add unmap_range_in_pgtbl & free_page_table
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Summary
This PR adds initial AArch64 EL1 4KB paging support and validates it by creating a runtime linear map after heap initialization.
It extends the MMU implementation with L1/L2/L3 page-table traversal, 4KB page descriptors, runtime page-table allocation, range map/unmap helpers, and recursive page-table cleanup. The PR also switches
TTBR1_EL1to a runtime-built linear map and increases the QEMU virt64 AArch64 heap size to support additional page-table allocations.Key Changes
Testing
Notes