Add reference to verilog-instance plugin in the README#149
Conversation
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Hi Antoine, I have a Vim function that does something similar to what you accomplish with your plugin, although mine is much simpler and would not support multiple ports per line. I feel that my plugin should include this functionality, but I have not added my function because it is too simple. I intend to implement such functionality in the future, but I would like to have as following:
If you feel like implementing this functionality (in Vim Language, not Python please) then I would love to integrate that work into this plugin. But because the functionality you are sharing in your plugin will eventually conflict with this plugin, I feel that it does not make sense to include such reference in the documentation. Hope you understand my reasoning. P.S. I've recently been a father, so please expect some delay in my updates. |
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Hi Vitor, First, congratulations on your baby :) Then, regarding verilog-instance, I completely understand your reasoning.
In conclusion, I am going to keep verilog-instance alive until it is merged in verilog_systemverilog. Cheers, |
Hi Vitor,
I just added this vim plugin:
https://github.com/antoinemadec/vim-verilog-instance
This creates SystemVerilog port instantiation from port declaration.
It is saving me a lot of time when I code in Verilog.
I have been using it for years now and I just found the courage to add features, re write it and release it to the world.
I was wondering if you could add it to the "Other vim plugins for Verilog/SystemVerilog" section of verilog_systemverilog's README ?
Also, feel free to report bugs or give me advice to make the plug-in clearer and cleaner.
Thanks in advance,
Antoine