feat: specialized horizontal row layout for decoupling capacitor partitions#51
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chengyixu wants to merge 2 commits intotscircuit:mainfrom
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feat: specialized horizontal row layout for decoupling capacitor partitions#51chengyixu wants to merge 2 commits intotscircuit:mainfrom
chengyixu wants to merge 2 commits intotscircuit:mainfrom
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Implements a specialized packing solver for decoupling capacitor partitions (partitionType === "decoupling_caps"). Instead of using the generic PackSolver2 algorithm which can produce messy scattered layouts, caps are arranged in a clean horizontal row — matching the "official layout" style shown in issue tscircuit#15. Changes: - Add DecouplingCapsPackingSolver: arranges caps left-to-right in a row, centered at x=0, all at rotation 0 so y+/y- pins align along a horizontal power/ground rail. Respects decouplingCapsGap over chipGap when set. - Update PackInnerPartitionsSolver to dispatch to DecouplingCapsPackingSolver for decoupling_caps partitions instead of the generic solver. - Add 5 unit tests for DecouplingCapsPackingSolver (placement, centering, gap config, visualization). - Add 2 integration tests verifying the full LayoutPipelineSolver pipeline correctly identifies and lays out decoupling cap groups. Closes tscircuit#15 Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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Expand inline object literals to multi-line and collapse short .map() call to single line to satisfy biome formatter requirements. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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The The remaining This test was already failing on main before this PR (see: main branch CI). It is unrelated to the |
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Summary
Implements a
DecouplingCapsPackingSolverthat arranges decoupling capacitors in a clean horizontal row, resolving the messy layout shown in issue #15.Before: Generic
PackSolver2packing scatters decoupling caps in a 2D cluster with inconsistent orientations.After: Caps are arranged in a clean left-to-right horizontal row (matching the "official layout" image in the issue) — all at rotation 0, evenly spaced, centered at the partition origin. Their y+/y- pins align along the same horizontal power/ground rail for clean routing.
Changes
lib/solvers/PackInnerPartitionsSolver/DecouplingCapsPackingSolver.ts— new solver: sorts caps by ID, places them in a horizontal row centered at x=0, respectsdecouplingCapsGapoverchipGapwhen setlib/solvers/PackInnerPartitionsSolver/PackInnerPartitionsSolver.ts— dispatches toDecouplingCapsPackingSolverforpartitionType === \"decoupling_caps\"partitionstests/PackInnerPartitionsSolver/DecouplingCapsPackingSolver.test.ts— 5 unit tests (single cap, row ordering, centering, gap config, visualization)tests/PackInnerPartitionsSolver/DecouplingCapsIntegration.test.ts— 2 integration tests verifying the full LayoutPipelineSolver pipeline with a synthetic MCU + caps circuitTest plan
bun test tests/PackInnerPartitionsSolver/)bun test)decoupling_capspartition are placed in a sorted horizontal rowdecouplingCapsGapis respected overchipGap/claim #15
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Closes #15