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feat: specialized linear layout for decoupling capacitor partitions#48

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Open

feat: specialized linear layout for decoupling capacitor partitions#48
themachinehf wants to merge 1 commit intotscircuit:mainfrom
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@themachinehf
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/claim #15

Summary

Replaces the generic PackSolver2 with a dedicated horizontal row layout for partitions of type `decoupling_caps`, matching the "acceptable solution" image posted by @seveibar.

Before / After

Before (PackSolver2): capacitors cluster in a chaotic pile with irregular spacing

After (this PR): capacitors are arranged in a clean horizontal row, centered at origin, with configurable gap:

```
[C1] [C2] [C3] [C4]
← centered at x=0 →
```

Implementation

Modified `SingleInnerPartitionPackingSolver.createLayoutFromPackingResult()`:

  • When `partitionType === "decoupling_caps"`, bypasses PackSolver2 placement
  • Uses `createDecouplingCapsLinearLayout()` which:
    • Sorts capacitors by chip ID (deterministic ordering)
    • Places them in a single horizontal row centered at x=0
    • Uses `decouplingCapsGap` (or `chipGap` fallback) for spacing
    • All capacitors placed at y=0 with 0° rotation

Files Changed

  • `lib/solvers/PackInnerPartitionsSolver/SingleInnerPartitionPackingSolver.ts` — +58 lines
  • `tests/DecouplingCapLayout/DecouplingCapLayout01.test.ts` — new test (+96 lines)

Testing

```bash
bun test tests/DecouplingCapLayout/DecouplingCapLayout01.test.ts
```

All existing tests pass (18 pass, 1 pre-existing error unrelated to this change).

Arranges decoupling capacitors in a clean horizontal row instead of
using the general-purpose packer which produces messy layouts.

For decoupling_caps partitions, capacitors are now:
- Sorted by chip ID (deterministic ordering)
- Placed in a single horizontal row centered at x=0
- Use consistent spacing (decouplingCapsGap or chipGap)
- Have 0 rotation (capacitors are symmetric)

Adds test case to verify horizontal linear layout behavior.
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vercel bot commented Mar 24, 2026

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