feat: specialized linear layout for decoupling capacitors#45
Open
mendarb wants to merge 2 commits intotscircuit:mainfrom
Open
feat: specialized linear layout for decoupling capacitors#45mendarb wants to merge 2 commits intotscircuit:mainfrom
mendarb wants to merge 2 commits intotscircuit:mainfrom
Conversation
When a partition is tagged as `decoupling_caps`, bypass the general PackSolver2 and instead arrange capacitors in a clean horizontal row sorted by chip ID. This eliminates the messy overlapping layout that the generic packing algorithm produces for these components. Three changes make this work end-to-end: 1. IdentifyDecouplingCapsSolver: relax the rotation constraint so 2-pin components without explicit `availableRotations` are still candidates (the y+/y- pin check already confirms orientation). Add transitive net lookup so a cap pin strongly connected to a chip pin inherits that pin's net — needed when the circuit wires cap.pin1 directly to a chip IOVDD pin and the V3_3 net is on the chip side of the connection. 2. getInputProblemFromCircuitJsonSchematic: infer `isGround` and `isPositiveVoltageSource` flags from well-known net names (GND, Vxx, VDD, VCC, etc.) so the decoupling-cap net-pair validation works without manual annotation. 3. SingleInnerPartitionPackingSolver: new `createLinearDecouplingCapLayout` early-returns a deterministic horizontal row for decoupling_caps partitions, with configurable gap via `decouplingCapsGap`. Tested on the RP2040 circuit: 0 overlaps, caps in clean rows. Closes tscircuit#15 Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
|
@mendarb is attempting to deploy a commit to the tscircuit Team on Vercel. A member of the Team first needs to authorize it. |
The test was importing from the .page.tsx file which transitively pulled in circuit-to-svg (via LayoutPipelineDebugger), causing a missing export error. Extracted the problem data to a standalone .ts file so tests can import it without triggering UI dependency resolution. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
/claim #15
Summary
IdentifyDecouplingCapsSolverworks out of the box without manualisGround/isPositiveVoltageSourceannotationC12.pin1 -> U3.IOVDD1) correctly inherit the chip pin's net (V3_3) for classificationChanges
SingleInnerPartitionPackingSolverWhen
partitionType === "decoupling_caps", bypassesPackSolver2and uses a newcreateLinearDecouplingCapLayout()method that:decouplingCapsGap)IdentifyDecouplingCapsSolveravailableRotationsare now valid candidates (thepinsOnOppositeYSidescheck already confirms vertical orientation)getNetIdsForPinTransitive(): when a cap pin has no direct net but is strongly connected to a chip pin, it inherits that chip pin's net -- this is needed for the common pattern whereC12.pin1 -> U3.IOVDD1andU3.IOVDD1 -> V3_3getInputProblemFromCircuitJsonSchematicisGroundandisPositiveVoltageSourcefrom net names (GND, Vxx, VDD, VCC, etc.)Test plan
tests/DecouplingCapLayout/DecouplingCapLayout01.test.ts:decoupling_capstype__snapshots__/DecouplingCapLayout01_final.svgfor visual verificationbun run format:checkpassesResults on RP2040 circuit
Before: 4 chip overlaps (U3-C14, C10-C7, C10-C12, C19-C15)
After: 0 overlaps -- IOVDD caps (C8, C12, C13, C14, C15, C19) in one clean row, DVDD caps (C7, C18) in another
Generated with Claude Code