Specialized Layout for Decoupling Capacitors

[Drgonzoh]

This PR implements a specialized layout algorithm for decoupling capacitors.

Key changes:

1. Updated IdentifyDecouplingCapsSolver to record the specific pin connections between decoupling capacitors and their main chips.
2. Modified ChipPartitionsSolver to keep decoupling capacitors in the same partition as their main chip, rather than separating them into a separate partition.
3. Enhanced SingleInnerPartitionPackingSolver to handle decoupling capacitors specially by combining them with their main chip into a single 'macro-component' for the packer.
4. Implemented specialized relative placement for decoupling capacitors near the pins they decouple, ensuring they are placed cleanly outside the main chip.

References #15

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