feat: integrate overlap resolution solver with voltage-aware biasing

[769066112-ops]

Summary

Fixes #12 - Improves layout by integrating the existing OverlapResolutionSolver into the pipeline and enhancing it with voltage-aware biasing.

Changes

Pipeline Integration

• Added OverlapResolutionSolver as a new pipeline phase after PartitionPackingSolver
• Updated getOutputLayout() to prefer the overlap-resolved layout
• Updated visualize() and preview() to show resolved layout

Overlap Resolution Improvements

• Voltage-aware biasing: VCC-connected chips are biased upward, GND-connected chips biased downward, following conventional schematic conventions
• Force damping: Progressive damping over iterations for stable convergence
• Layout re-centering: After resolution, the layout is re-centered around the origin
• Performance caching: Connected pairs and chip-net mappings are cached to avoid redundant computation

Tests

• Added test verifying overlap resolution phase integrates into the pipeline and produces zero-overlap layouts
• Added test verifying voltage biasing correctly positions VCC caps above GND caps

How It Works

The solver runs a force-directed algorithm:

1. Repulsion: Overlapping chips are pushed apart along the axis of minimum overlap
2. Attraction: Strongly connected chips are pulled together to keep the layout compact
3. Voltage bias: Chips connected to positive voltage nets get a gentle upward force; ground-connected chips get a downward force
4. Damping: Forces are progressively damped for convergence stability
5. Re-centering: Final layout is centered at the origin

All existing tests continue to pass.

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