EVPIX-RV32: 5-Stage Custom RISC-V SoC with Integrated IPU and TinyML Support for Real-Time Edge-Vision AI Acceleration: RTL-to-GDSII Design, Verification, Basys-3 Artix-7 FPGA Prototyping and SkyWater 130-nm CMOS ASIC was implementation

Synthesizable RV32IM Audio SoC featuring a centralized AMBA AXI4-Lite Router Matrix, AXI-to-APB Bridge, 1KB Data SRAM, and PWM engine. Timing-closed and physical layout verified via OpenLane (Sky130).

Fixed-point MAC accelerator designed to study ASIC timing closure, pipelining, and accumulation feedback in Sky130.

Simple Systolic array implementation

Design of a 10-bit R-2R DAC using the open-source SkyWater 130nm PDK. Includes schematics, layout files, and a Python environment for metric evaluation (for educational purposes).

Data-driven EDA and ML-based predictive modelling of real VLSI design metrics from an OpenLane RTL-to-GDSII flow. 8-bit ALU on Sky130 PDK.

Automated SKY130 DRC flow using KLayout, Python, and TCL to run custom design-rule checks, parse XML results, and generate an HTML violation dashboard.

RTL-to-GDSII physical design flow of PicoRV32a RISC-V processor using OpenLANE and Sky130 PDK. Completed under NASSCOM FutureSkills Prime program. Synthesis, floorplan, placement, CTS, routing, DRC/LVS clean, GDSII generated.