Designed a high-speed two-stage dynamic comparator for SAR ADCs using a StrongARM latch with dynamic biasing. Achieved 1.024 GHz speed, 90.26 ps delay, 5.23 µV noise, and 52.48 fJ energy, with a FoM of 2.18, proving suitability for high-speed ADCs.
Design and Simulation of Fully DIfferential 8-bit SAR ADC
Example describing the basic functionality of the ADC in tinyAVR 1-series.
An introduction to adc's on megaavr 0 series
MTB code example
100KSPS 8-bitSuccessive Approximation Register (SAR) analog-to-digital converter (ADC) for Low-power Applications (UNIC-CASS program by IEEE CASS)
MTB code example
MTB code example
MTB code example
Cooperated by Chen Xuanren, Yuan Yiming, Zhang Changxiang and Zhu Yanxiang.
MTB code example
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