Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization
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Updated
Jan 22, 2025 - Verilog
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neural-network-hardware
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Ultra-low-latency Ternary Neural Network inference engine for HFT alpha generation, optimized for an ultra-budget 1,120-LUT Renesas FPGA. Features a fully unrolled combinatorial popcount tree achieving 2-cycle deterministic execution without hardware multipliers, paired with an ESP32-S3 hardware-software co-design.
fpga esp32 rtl verilog low-latency hft hardware-acceleration quantitative-trading digital-design system-on-chip high-frequency-trading bnn binary-neural-networks bnn-fpga edge-ai tiny-ml esp32-s3 neural-network-hardware machine-learning-inference
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Updated
Jun 2, 2026 - Verilog
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