Virtual development board for HDL design

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

Modelsim QEMU Unicorn integration via the FLI

Demo showing Modelsim calling Python's Numpy and Matplotlib libraries

Modelsim Inter Process Communication using the FLI

Fork to be able to use the -fli parameter with input_raspicam

Adding strong RNG to Modelsim via the FLI

Modelsim serial port interface via the FLI

Modelsim generating a fern and sending the coordinates via a socket to a display program

Demo showing Modelsim calling Python Contraint Solver

A demonstration of the use case of fli building a cli based file system manager

Tiny standalone FLI/FLC → PNG sequence converter (40 KB, no dependencies, c++ cli fli and flc converter)