muhammadtalhasami / Axi4_lite_interface Star 3 Code Issues Pull requests This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used . vivado system-verilog verilator axi4 axi4-lite axi4-protocol axi4-lite-interface axi4-lite-system-verilog Updated May 4, 2024 SystemVerilog
logicbyvini / advanced-digital-logic-lib Star 2 Code Issues Pull requests SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence). dsp systemverilog soc uvm risc-v genus riscv32 asic-verification axi4 axi4-lite axi4-protocol asic-design xcelium neorv32 uvm-verification innovus cadence-xcelium axi4-lite-system-verilog uvm-testbench genus-synthesis Updated Feb 5, 2026