GitHub - teotro/QC-TEE: Verilog implementation of the hardware architecture designed to protect quantum circuits in superconducting quantum machines

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
AES		AES
fifo		fifo
memory		memory
python		python
shake256		shake256
tb		tb
uart		uart
clog2.v		clog2.v
dec_enc_engine.v		dec_enc_engine.v
main_controller.v		main_controller.v
shifter.v		shifter.v
top_with_fifo.v		top_with_fifo.v
uart_top_no_fifo.v		uart_top_no_fifo.v