GitHub - tba109/verilib: My personal library of odds and ends Verilog functions I find useful.

tba109 / verilib Public

My personal library of odds and ends Verilog functions I find useful.

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Name		Name	Last commit message	Last commit date
Latest commit History 32 Commits
bitstream_counter		bitstream_counter
checker		checker
clip		clip
clip_signed		clip_signed
cmp		cmp
config_ind		config_ind
crc16_16b_parallel		crc16_16b_parallel
crc16_8b_parallel		crc16_8b_parallel
crs_master		crs_master
dff_p		dff_p
err_mngr		err_mngr
fcr_ctrl_32b		fcr_ctrl_32b
fcr_ctrl_72b		fcr_ctrl_72b
fncs		fncs
ft232r_hs		ft232r_hs
ft232r_proc_buffered		ft232r_proc_buffered
gated_integrator		gated_integrator
gaus_rand		gaus_rand
hs_adapter_run		hs_adapter_run
hstm		hstm
i2c_byte		i2c_byte
i2c_master		i2c_master
iter_integer_linear_cal		iter_integer_linear_cal
multivib		multivib
negedge_detector		negedge_detector
one_shot		one_shot
pedge_req		pedge_req
pline		pline
posedge_detector		posedge_detector
pulse_gen		pulse_gen
ram_delay		ram_delay
ram_dual		ram_dual
rand_uniform_8b		rand_uniform_8b
rate_scaler		rate_scaler
rbd_task_ctrl		rbd_task_ctrl
rs232_des		rs232_des
rs232_des_old		rs232_des_old
rs232_ser		rs232_ser
rs232_ser_old		rs232_ser_old
rst_gen		rst_gen
serial_ck		serial_ck
serial_rx		serial_rx
serial_tx		serial_tx
sign_ext		sign_ext
spi_master		spi_master
sync		sync
task_reg		task_reg
template		template
true_dual_port_ram_dual_clock		true_dual_port_ram_dual_clock
uart_proc		uart_proc
uart_proc_hs		uart_proc_hs
verilib_8b10b		verilib_8b10b
watchdog		watchdog
word_sync		word_sync
xfpga_regs		xfpga_regs
README.txt		README.txt

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Tyler Anderson Tue Nov 13 17:22:10 EST 2018

Verilog modules I use very often. Useful. Add testbenches at some point.

My personal library of odds and ends Verilog functions I find useful.

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