Add maxnreg autotuning to Mamba-3 Triton kernels#905
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ChrisLundquist
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Triton's HIP backend does not recognize the maxnreg keyword argument (added for NVIDIA in PR state-spaces#905), raising: KeyError: 'Keyword argument maxnreg was specified but unrecognised' Add _maxnreg() helper that returns {} on HIP and {maxnreg: value} on CUDA, and use **_maxnreg(r) in all autotune Config constructors. Verified on AMD RX 9070 XT (gfx1201): - All math utils: PASS (cos/sin err=0, tanh err=1.8e-7) - mamba3_siso_fwd kernel: PASS - angle_dt_fwd kernel: PASS - mamba3_siso_combined pipeline: PASS - Forward throughput: 3.9M tok/s at seqlen=1024 Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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ChrisLundquist
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Apr 12, 2026
Triton's HIP backend does not recognize the maxnreg keyword argument (added for NVIDIA in PR state-spaces#905), raising: KeyError: 'Keyword argument maxnreg was specified but unrecognised' Add _maxnreg() helper that returns {} on HIP and {maxnreg: value} on CUDA, and use **_maxnreg(r) in all autotune Config constructors. Verified on AMD RX 9070 XT (gfx1201): - All math utils: PASS (cos/sin err=0, tanh err=1.8e-7) - mamba3_siso_fwd kernel: PASS - angle_dt_fwd kernel: PASS - mamba3_siso_combined pipeline: PASS - Forward throughput: 3.9M tok/s at seqlen=1024 Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Add
maxnreg(max register count) as an autotuning dimension ([None, 128, 256]) to all Mamba-3 SISO forward and backward Triton kernels; On SM100 (Blackwell/B200/B300), the Triton compiler may default to a low register count (e.g. 32 or 168 out of 255 available) whenmaxnregis unspecified, causing excessive register spilling