GitHub - satishkumar1221/verilog-dump · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 20 Commits
svfd		svfd
tutorial		tutorial
decoder_example.v		decoder_example.v
dffa.v		dffa.v
fifo.v		fifo.v
fsm.v		fsm.v
latch.v		latch.v
lfsr.v		lfsr.v
mixed.v		mixed.v
priority_enc.v		priority_enc.v
sv_examples.v		sv_examples.v

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SystemVerilog 92.3%
Verilog 7.7%