Prepare qcom-next based on tag 'Linux 6.19-rc6' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git #182
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When both USB and DP PHY modes are enabled simultaneously on the same QMP USBC PHY, it can lead to hardware misconfiguration and undefined behavior. This happens because the PHY resources are not designed to operate in both modes at the same time. To prevent this, introduce a mutual exclusion check between USB and DP PHY modes. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-10-dc5edaac6c2b@oss.qualcomm.com/
Add dedicated headers for DP v2 PHY, including QSERDES COM and TX/RX register definitions. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com> Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-11-dc5edaac6c2b@oss.qualcomm.com/
…de support Add QCS615-specific configuration for USB/DP PHY, including DP init routines, voltage swing tables, and platform data. Add compatible "qcs615-qmp-usb3-dp-phy". Note: SW_PORTSELECT handling for orientation flip is not implemented due to QCS615 fixed-orientation design and non-standard lane mapping. Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-12-dc5edaac6c2b@oss.qualcomm.com/
The Qualcomm SA8775P platform comes with 2 DisplayPort controllers for each mdss. Update controller id for DPTX0 and DPTX1 of mdss1. Fixes: dcb380d ("drm/msm/dp: Add DisplayPort controller for SA8775P") Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com> Link: https://lore.kernel.org/all/20251125105622.1755651-2-quic_mkuntuma@quicinc.com/
The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states VDDI=1.65V~1.95V, so set sufficient voltage for panel nt37801. Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20251023080609.1212-2-yuanjie.yang@oss.qualcomm.com/#r Signed-off-by: Yash Gupta <quic_ygupt@quicinc.com>
…o 1000ms EDID interrupt was coming 600-650 ms after HPD interrupt, resulting into EDID read timeout and default resolution of 1024x768 on display. Signed-off-by: Gopi Botlagunta <venkata.botlagunta@oss.qualcomm.com> Link: https://lore.kernel.org/all/20251121-hdmibridge-v1-1-14c63890f362@oss.qualcomm.com/
…on QCS8300 Document DSI controller and phy on QCS8300 platform. Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> Link: https://lore.kernel.org/all/20251125013302.3835909-4-quic_amakhija@quicinc.com/ Signed-off-by: Arpit Saini <arpisain@qti.qualcomm.com>
… DSI CTRL Document the DSI CTRL on the QCS8300 Platform. Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> Link: https://lore.kernel.org/all/20251125013302.3835909-3-quic_amakhija@quicinc.com/ Signed-off-by: Arpit Saini <arpisain@qti.qualcomm.com>
… DSI PHY Document the DSI PHY on the QCS8300 Platform. Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> Link: https://lore.kernel.org/all/20251125013302.3835909-2-quic_amakhija@quicinc.com/ Signed-off-by: Arpit Saini <arpisain@qti.qualcomm.com>
Turn on the switch and use virtual planes by default, enhancing utilisation of the display pipelines. It is still possible to use legacy implementation by using `msm.dpu_use_virtual_planes=false` kernel boot parameter. Link:https://lore.kernel.org/all/20250514-dpu-enable-virt-planes-v1-1-bf5ba0088007@oss.qualcomm.com/ Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Add support for the merge3d block on sc7280 which will allow merge of streams coming from two layer mixers routed to single non DSC interface. This change helps to support larger buffer width which exceeds max_linewidth of 2400. Link:https://lore.kernel.org/all/20251124-merge3d-sc7280-v1-1-798d94211626@oss.qualcomm.com/ Fixes: 591e34a ("drm/msm/disp/dpu1: add support for display for SC7280 target") Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Currently valid mode checks are only for hdisplay and vdisplay, add htotal and vtotal to filter only specific modes. Link:https://lore.kernel.org/lkml/20251126-lt9611uxc-modes-v2-1-34bf9b351921@oss.qualcomm.com/ Signed-off-by: Nilesh Laad <nilesh.laad@oss.qualcomm.com> Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Add 3840x2160@30 mode in lt9611uxc modes to add support for 4K@30 resolution. Link:https://lore.kernel.org/r/20251126-lt9611uxc-4k30-v2-1-3de0ea58c24e@oss.qualcomm.com Signed-off-by: Nilesh Laad <nilesh.laad@oss.qualcomm.com> Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Add bindings for lt8713sx. Co-developed-by: Prahlad Valluru <vvalluru@qti.qualcomm.com> Signed-off-by: Prahlad Valluru <vvalluru@qti.qualcomm.com> Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com> Link: https://lore.kernel.org/all/20251228-lt8713sx-bridge-driver-v3-1-9169fbef0e5b@oss.qualcomm.com/
The lt8713sx is a Type-C/DP1.4 to Type-C/DP1.4/HDMI2.0 converter, with three configurable DP1.4/HDMI2.0/DP++ output interfaces and audio output interface. Driver is required for firmware upgrade in the bridge chip. Co-developed-by: Prahlad Valluru <vvalluru@qti.qualcomm.com> Signed-off-by: Prahlad Valluru <vvalluru@qti.qualcomm.com> Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com> Link: https://lore.kernel.org/all/20251228-lt8713sx-bridge-driver-v3-2-9169fbef0e5b@oss.qualcomm.com/
Enable Remoteproc cooling feature config. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Add CAMX overlay dts file for Talos boards. This change also enables the compilation of the CAMX overlay on Talos boards. Signed-off-by: Chandan Kumar Jha <cjha@qti.qualcomm.com>
… compatible For M.2 WLAN chips, there is no suitable DTS node to specify the firmware-name property. In addition, assigning firmware for the M.2 PCIe interface causes chips that do not use usecase specific firmware to fail. Therefore, abandoning the approach of specifying firmware in DTS. As an alternative, propose a static lookup table mapping device compatible to firmware names. Currently, only WCN6855 HW2.1 requires this. For details on usecase specific firmware, see: https://lore.kernel.org/all/20250522013444.1301330-3-miaoqing.pan@oss.qualcomm.com/. Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04685-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1 Fixes: edbbc64 ("wifi: ath11k: support usercase-specific firmware overrides") Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com> Link: https://lore.kernel.org/linux-wireless/20251204071100.970518-2-miaoqing.pan@oss.qualcomm.com/
Currently, the FBC image is a non-standard ELF file that contains a single
ELF header, followed by segments for SBL, and WLAN FW. However, TME-L
(Trust Management Engine Lite) supported devices (eg. QCC2072) requires
separate ELF headers for SBL and WLAN FW segments due to TME-L image
authentication requirement.
Current image format contains two sections in a single binary:
- First 512KB: ELF header + SBL segments
- Remaining: WLAN FW segments
The TME-L supported image format contains two sections with two elf
headers in a single binary:
- First 512KB: First ELF header + SBL segments
- Remaining: Second ELF header + WLAN FW segments
Download behavior:
- Legacy: 1. First 512KB via BHI (ELF header + SBL)
2. Full image via BHIe
- TME-L: 1. First 512KB via BHI (First ELF header + SBL)
2. Remaining via BHIe (Second ELF header + WLAN FW segments)
Add standard_elf_image flag to mhi_controller_config to indicate TME-L
supported image format. When set, MHI skips the first 512KB during WLAN FW
download over BHIe as it is loaded in BHI phase.
Reviewed-by: Baochen Qiang <quic_bqiang@quicinc.com>
Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://lore.kernel.org/mhi/20251201-wlan_image_load_skip_512k-v3-1-bedb5498a58a@oss.qualcomm.com/
Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Currently offset of PCI window register address is defined as 0x310c which is same across existing chips. However QCC2072 has a different offset 0x3278. In order to make the window selection logic work for QCC2072 as well, change to initialize this parameter per device at the probe time. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Link: https://lore.kernel.org/linux-wireless/20251218-ath12k-support-qcc2072-v1-1-87928cf8e547@oss.qualcomm.com/ Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
The entry of REO CMD ring of existing chips has a 64 bit TLV header, hence below functions take a 64 bit TLV assumption by default reo_init_cmd_ring reo_cmd_encode_hdr However this is not the case for QCC2072 of which the TLV is 32 bit, meaning above functions don't work for it. Rename/refactor above functions to prepare for QCC2072 support: Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Link: https://lore.kernel.org/linux-wireless/20251218-ath12k-support-qcc2072-v1-2-87928cf8e547@oss.qualcomm.com/ Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
The entry of REO status ring of existing chips has a 64 bit TLV header, however this is not the case for QCC2072 of which the TLV is 32 bit. Refactor above functions to prepare for QCC2072 support, this is done by removing TLV length assumption and offloading TLV decoding work to a newly added callback _reo_status_dec_tlv_hdr. This way each chip can register its own handler hence can do the work accordingly. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823 Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Link: https://lore.kernel.org/linux-wireless/20251218-ath12k-support-qcc2072-v1-3-87928cf8e547@oss.qualcomm.com/ Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
…tion For single pdev device like WCN7850/QCC2072, preferred_hw_mode is initialized to WMI_HOST_HW_MODE_SINGLE. Later when firmware sends supported modes to host, each mode is compared with the initial one and if the priority of the new mode is higher, update the parameter and store mode capability. For WCN7850, this does not result in issue, as one of the supported mode indeed has a higher priority. However the only available mode of QCC2072 at this stage is WMI_HOST_HW_MODE_SINGLE, which fails the comparison, hence mode capability is not stored. Subsequently driver initialization fails. Fix it by accepting a mode with the same priority. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Link: https://lore.kernel.org/linux-wireless/20251218-ath12k-support-qcc2072-v1-4-87928cf8e547@oss.qualcomm.com/ Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
…parsing For single pdev device, 320 MHz bandwidth support is reported only in capability of WMI_HOST_HW_MODE_SINGLE mode, hence commit d4e244c ("wifi: ath12k: enable 320 MHz bandwidth for 6 GHz band in EHT PHY capability for WCN7850") relaxed the condition check in ath12k_wmi_tlv_mac_phy_caps_ext() to allow SINGLE mode getting parsed in ath12k_wmi_tlv_mac_phy_caps_ext_parse(). Since SINGLE mode is not assumed to be preferred, the function returns unconditionally after parsing 320 MHz support. This works for WCN7850 because it prefers another mode indeed, while it breaks QCC2072 since it prefers SINGLE mode. Due to the unconditional return, the subsequent EHT parsing is skipped. Consequently EHT related features are disabled. Refactor it by moving 320 MHz parsing to ath12k_wmi_tlv_mac_phy_caps_ext(), before the mode checking. This makes the code more straightforward, and work for both WCN7850 and QCC2072. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Link: https://lore.kernel.org/linux-wireless/20251218-ath12k-support-qcc2072-v1-5-87928cf8e547@oss.qualcomm.com/ Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Currently ath12k_pull_mac_phy_cap_svc_ready_ext() assumes only one band supported in each phy, hence it skips 5 GHz band if 2 GHz band support is detected. This does not work for device which gets only one phy but has both bands supported, such as QCC2072. Change to check each band individually to fix this issue. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Link: https://lore.kernel.org/linux-wireless/20251218-ath12k-support-qcc2072-v1-6-87928cf8e547@oss.qualcomm.com/ Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Add hardware registers and populate hw_regs field in ath12k_wifi7_hw_ver_map for QCC2072. Note for some registers not defined and not used by QCC2072, a magic value is assigned. Also populate other fields to be the same with WCN7850. Among them, however, QCC2072 requires different HAL ops and descriptor size, both will be updated in upcoming patches. Tested-on: QCC2072 hw1.0 PCI WLAN.COL.1.0-01560-QCACOLSWPL_V1_TO_SILICONZ-1 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.1.c5-00302-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.115823.3 Signed-off-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Link: https://lore.kernel.org/linux-wireless/20251218-ath12k-support-qcc2072-v1-7-87928cf8e547@oss.qualcomm.com/ Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Add new SCM call to program secure camera qos settings. For each NIU camera driver can call this scm API which need each NIU's register offsets, value and number of registers offset that need to be programmed. Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
…client ids Physical client IDs instead of virtual client IDs are used for qcom new platforms in the Inter Process Communication Controller (IPCC) driver as virtual physical mapping logic is removed in HW. Add the bindings. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20250922-ipcc-header-v1-1-f0b12715e118@oss.qualcomm.com/
Add support for the kaanapali platform by re-using the SM8550 definitions and using the vpu4 ops. Move the configurations that differs in a per-SoC platform header, that will contain SoC specific data. Link: https://lore.kernel.org/all/20251017-knp_video-v2-8-f568ce1a4be3@oss.qualcomm.com/ Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Add support for SYSTEM_RESET2 vendor-specific resets in qcs615-ride as reboot-modes. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20250922-arm-psci-system_reset2-vendor-reboots-v15-14-7ce3a08878f1@oss.qualcomm.com Signed-off-by: Song Xue <quic_songxue@quicinc.com> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
# Conflicts: # Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
# Conflicts: # Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile # arch/arm64/boot/dts/qcom/talos.dtsi
# Conflicts: # include/linux/firmware/qcom/qcom_scm.h
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Name SHA Commits
tech/bsp/clk dcb6c1e 20
tech/security/firmware-smc a50984a 2
tech/bsp/soc-infra 2949741 9
tech/bsp/remoteproc 68d1bd1 19
tech/bus/peripherals 486bcf7 1
tech/bus/pci/all d9f9599 8
tech/bus/usb/dwc 49ac8e0 2
tech/bus/usb/phy 9e7d778 13
tech/debug/hwtracing 88c50d8 27
tech/pmic/misc 91e88b9 16
tech/pmic/regulator 81fc8fb 6
tech/mem/iommu 4cff31b 3
tech/mm/audio/all ce10fd3 4
tech/mm/camss d1d2c38 3
tech/mm/drm 9bb86be 28
tech/mm/fastrpc f55ee11 8
tech/mm/video 4871417 16
tech/mm/gpu 1651b6d 5
tech/mproc/rpmsg c3875d9 1
tech/net/ath 977ecee 22
tech/net/eth c280d7e 1
tech/net/bluetooth 46c6608 5
tech/pm/power 7b7e779 7
tech/pm/thermal 363f414 3
tech/security/crypto fa6b06a 11
tech/storage/all ba8c93d 6
tech/all/dt/qcs6490 87b5b8c 7
tech/all/dt/qcs9100 b170120 17
tech/all/dt/qcs8300 03de422 27
tech/all/dt/qcs615 648a531 11
tech/all/dt/hamoa e571479 16
tech/all/dt/glymur b6ddb1f 27
tech/all/dt/kaanapali f901c31 5
tech/all/dt/pakala b4ebc9f 9
tech/all/config e737dd0 37
tech/overlay/dt 50f2b36 15
tech/all/workaround 65d2481 4
tech/mproc/all d19a4c1 5
tech/noup/debug/all 1c86d19 5