feat(jit): add RISC-V 64 and AArch64 JIT backends

[CN-TangLin]

Summary

This PR adds native JIT compiler backends for RISC-V 64-bit and AArch64 (ARM64) architectures, and refactors the existing x86_64 backend into a separate file to unify the code organization.

Why not use the existing Cranelift feature?

The cranelift feature (behind #[cfg(feature = "cranelift")]) provides multi-architecture JIT via the Cranelift codegen framework, which is the right tool for user-space applications. However, for OS kernel integration scenarios, a native JIT backend is preferred:

1. Zero external dependencies: The native backends use only the byteorder crate (already in the dependency tree). Cranelift adds 5 additional crates (cranelift-codegen, cranelift-frontend, cranelift-jit, cranelift-module, cranelift-native) which are unsuitable for no_std kernel environments.

2. Lighter weight: The native backends generate compact machine code directly without going through an IR layer. This means faster compilation and smaller code footprint, which matters in resource-constrained embedded or kernel contexts.

3. Kernel compatibility: The no_std variant of JitMemory::new() already supports caller-provided executable memory — this is essential for kernels that manage their own page tables and memory protection. The Cranelift JIT path assumes a user-space allocator.

In short: Cranelift serves user-space well; native backends serve kernel/embedded use cases. They complement rather than replace each other.

On maintainership

These backends are derived from and actively used in the StarryOS kernel (https://github.com/rcore-os/tgoskits), where they have been running eBPF programs on RISC-V and AArch64 hardware for months. We are committed to maintaining them in rbpf as well — we will respond to issues, keep them up to date with eBPF ISA changes, and fix bugs as they arise.

Changes (3 commits)

1. feat(jit): add RISC-V 64-bit JIT backend and multi-arch dispatch

   • New file src/jit_riscv64.rs — full RISC-V 64 JIT compiler
   • Register mapping: BPF R0-R4→t0-t4, R5→t5, R6-R10→s1-s5
   • Stack frame: 512B BPF stack + 48B callee-saved
   • Supports all ALU32/ALU64, JMP64, LD/ST/STX, CALL, EXIT
   • JMP32 partial (JEQ32 only, others return error)
   • LD_ABS/LD_IND, TAIL_CALL, ST_XADD return error
   • Uses AUIPC+JALR for long-range jump resolution
   • src/lib.rs: pub mod jit for external access

2. feat(jit): add AArch64 (ARM64) JIT backend

   • New file src/jit_aarch64.rs — full AArch64 JIT compiler
   • Register mapping: BPF R0-R5→x0-x5, R6-R9→x19-x22, R10→x25
   • Stack frame: 512B BPF stack + 64B callee-saved
   • Supports all ALU32/ALU64, JMP32/JMP64, LDX/ST/STX, CALL, EXIT
   • Uses native REV16/REV32/REV64 for byte swaps
   • Uses MOVZ+MOVK sequence for 64-bit immediate loading
   • Jump resolution via MOVZ+MOVK×3+ADR+ADD+BR trampoline
   • #[cfg(feature = "std")] gated (uses libc::mprotect)

3. refactor(jit): extract x86_64 backend into separate file

   • Move x86_64 JIT from src/jit.rs into src/jit_x86_64.rs
   • jit.rs now contains only arch-agnostic infrastructure (JitMemory, constants, dispatch)
   • Unifies organization: one file per architecture
   • No functional changes to x86_64 JIT logic
   • Uses #[path] attributes for Rust 2024 edition module resolution

Regarding tests

I acknowledge that tests/ubpf_jit_x86_64.rs already provides comprehensive execution-level tests (95+ test functions) for the x86_64 JIT. The unit tests that were in the earlier separate PR (#151) have been removed from this submission — the existing integration test suite is more thorough and covers the entire eBPF ISA.

For the new RISC-V and AArch64 backends, we rely on real-hardware testing in the StarryOS kernel (QEMU virt machines for riscv64 and aarch64), and the existing interpreter tests which exercise the same code paths regardless of JIT backend.

Verification

• cargo clippy --all-features: zero warnings
• cargo test --all-features: all 117 unit tests + JIT integration tests pass
• Tested on StarryOS kernel: riscv64 (QEMU virt) and aarch64 (QEMU virt) hardware