feat: ARM target profiles with FPU capability threading

[avrabe]

Summary

• Add fpu: Option<FPUPrecision> to TargetSpec and thread it through the entire compilation pipeline (CLI → instruction selector → encoder → ELF builder → startup code)
• New target constructors: cortex_m3(), cortex_m4f(), cortex_m7dp() with correct triples and FPU settings
• New --target CLI flag (cortex-m3, cortex-m4, cortex-m4f, cortex-m7, cortex-m7dp) that implies --cortex-m for Cortex-M targets
• Target-aware float error messages: "target cortex-m3 has no FPU" vs "VFP encoding not yet implemented (target cortex-m4f has FPU)"
• ELF e_flags set to EF_ARM_ABI_FLOAT_HARD for hard-float targets
• Cortex-M startup emits CPACR FPU enable sequence (CP10+CP11 full access, DSB, ISB) when target has FPU
• ArmEncoder gains fpu field (prep for VFP instruction encoding in Task 4)

Prerequisite for #36 (anti-pinch test case requires VFP float support).

Test plan

• All 44 test suites pass (cargo test --workspace)
• cargo clippy --workspace --all-targets -- -D warnings clean
• cargo fmt --check clean
• f64 rejection tests updated to match new error message format
• New tests for cortex_m3, cortex_m4f, cortex_m7dp, cortex_m7 target parsing
• CI passes

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