Support for Cadence Xcelium simulator

[uge]

Adds basic support for Cadence Xcelium simulator.

Only verilog (not vhdl) tested.

[micprog]

I see you have support for verilog files, which is a great start. As bender is generally built to support vhdl files as well, and this simulator supports vhdl, it would be great to ensure compatibility here as well.

[uge]

We don't have any VHDL code internally to test with. If there is a public Bender repo with VHDL code and a simulation target, please refer me to it an I'll try to include the template.

[yvantor]

Hi @uge, we have a can_bus entirely written in VHDL. You can also find it integrated in Cheshire if you need an example with both Verilog and VHDL IPs.

[DanielKellerM]

Hi @uge I wanted to verify this so we can merge it. Can you advise how are you calling the output script from Bender with Xcelium?