Full Adder – SystemVerilog | Cadence Verification | Multi-Node PPA Analysis

Journal Publication Repository Design, Verification & Physical Synthesis of a 1-bit Full Adder across 18nm, 45nm, 90nm, and 180nm Technology Nodes

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Abstract

This repository contains the complete RTL-to-synthesis flow for a 1-bit Full Adder implemented in SystemVerilog. The design is verified using Cadence Xcelium (functional simulation) and synthesised using Cadence Genus across four CMOS technology nodes. Power, area, and delay (PPA) metrics are reported and compared.

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Repository Structure

fulladder_cadence/
├── rtl/
│   └── full_adder.sv           # SystemVerilog RTL (combinational)
├── tb/
│   └── tb_full_adder.sv        # Self-checking testbench (8 vectors)
├── sim/
│   ├── run_sim.sh              # Cadence Xcelium simulation script
│   ├── run_sim.tcl             # TCL simulation launcher
│   └── waves.sv                # SimVision waveform config
├── syn/
│   ├── genus_syn.tcl           # Cadence Genus synthesis (all nodes)
│   ├── constraints.sdc         # SDC timing constraints
│   ├── run_all_nodes.sh        # Batch synthesis across 4 nodes
│   └── parse_results.py        # PPA results parser
└── reports/
    ├── full_adder_schematic.png # Gate-level schematic diagram
    ├── full_adder_waveform.png  # Simulation waveform (all 8 vectors)
    ├── expected_results.md      # PPA reference table + methodology
    └── generate_visuals.py      # Python script for figure generation

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Full Adder Logic

sum  = a ⊕ b ⊕ cin
cout = (a·b) + (b·cin) + (a·cin)

Critical path: cin → sum (two series XOR gates)

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Gate-Level Schematic

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Simulation Waveform (All 8 Input Vectors)

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PPA Results Summary

Technology	Delay (ps)	Dynamic Power (µW)	Cell Area (µm²)
18nm	10–15	0.10–0.25	0.25–0.45
45nm	25–35	0.80–1.50	1.8–2.5
90nm	50–65	3.5–6.0	7.0–10.0
180nm	100–130	14–22	28–38

• Delay halves with each ~2× node shrink
• Dynamic power reduces ~100× from 180nm → 18nm
• Cell area reduces ~80–90× from 180nm → 18nm

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Tool Flow

Functional Simulation (Cadence Xcelium)

cd sim/
xrun -sv ../rtl/full_adder.sv ../tb/tb_full_adder.sv \
     -top tb_full_adder -access +rwc -timescale 1ns/1ps

Logic Synthesis (Cadence Genus)

cd syn/
# Single node (edit TECH_NODE inside genus_syn.tcl):
genus -batch -f genus_syn.tcl -log genus.log

# All 4 nodes at once:
./run_all_nodes.sh

View PPA Table

cd syn/
python3 parse_results.py

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Technology Nodes

Node	Architecture	Vdd (V)	Gate Length
18nm	FinFET	0.7–0.8	~7–10 nm eff
45nm	Bulk CMOS	1.0–1.1	~35–40 nm
90nm	Bulk CMOS	1.0–1.2	~65–75 nm
180nm	Bulk CMOS	1.8	~150–180 nm

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Citation

If you use this work in your research, please cite:

@misc{fulladder_multinode,
  title   = {Full Adder Design and PPA Analysis Across 18nm--180nm CMOS Nodes},
  author  = {nishaangelinem-coder},
  year    = {2026},
  url     = {https://github.com/nishaangelinem-coder/fulladdertest}
}