Verilog Vending Machine FSM

📝 Overview

This repository contains a Verilog implementation of a Vending Machine Controller. The project focuses on a Moore Finite State Machine capable of handling multiple denominations and managing "change" as carry-over credit for subsequent users.

🎯 Specifications

• Product Price: 3.0 Lei.
• Accepted Inputs: - m: 0.5 Lei (coin)
  • b: 1.0 Lei (banknote)
  • Both inputs can be active simultaneously (1.5 Lei increment).
• Output: out signal triggers when the balance ≥ 3.0 Lei.
• Credit Retention: Excess funds (0.5 or 1.0 Lei) are automatically transitioned into the starting credit for the next transaction.

⚙️ Logic Design

The machine operates on 9 states, where each state represents the accumulated balance in steps of 0.5:

• States q0–q5: Accumulation phase (0.0 to 2.5 Lei).
• State q6 (3.0 Lei): Dispense -> Reset to 0.0 balance.
• State q7 (3.5 Lei): Dispense -> Reset to 0.5 balance.
• State q8 (4.0 Lei): Dispense -> Reset to 1.0 balance.

State Transition Logic

The transition uses a concatenated control vector {b, m}:

{b, m}	Value Added	Logic
2'b01	+0.5	next_state = state + 1
2'b10	+1.0	next_state = state + 2
2'b11	+1.5	next_state = state + 3

🚀 Simulation

The included testbench (test_vending.v) validates:

1. Standard payment paths.
2. Concurrent input handling (b and m high at once).
3. Reset functionality.
4. Correct state fallback for credit retention.