kevin861222
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ๆๆฏ็่ช๏ผไบค้ๅคงๅญธ็ ็ฉถ็๏ผๆ็ๅฐ้ทๆฏๆธไฝ้ป่ทฏ่จญ่จ๏ผๅ ทๅ้ซ็็ทดๅบฆ็ Verilog ่ Python ใ
็ฎๅ้ๆบไบไธไบๅฐๆกไฝ็บๅญธ็ฟๆธไฝ้ป่ทฏ็ๅ้ก๏ผไปฅไธๆฏๆ่ช่ฑช็ไฝๅ๏ผ
SOC: FSIC Design
Memory controller: SDRAM controller
ML Accelerator: 4x4 TPU, Bit-serial-CIM-Convolution-IP
FPGA: AAML final proj
่ถ ่ฉณ็ดฐ ICLAB 2024 Spring ไฟฎ่ชฒๅฟๅพ & ไฟฎ่ชฒๆๅ๏ผๅซ่ณๆบๆด็
้ปๆงๆๆญ้ฝ็ๆๆ<้ฒ้ๅฏ็จๅผ้่ผฏ็ณป็ตฑ่จญ่จ่ๆ็จ>
Verilog 5
sparse matrix convolution accelerator with clock gate
Verilog 4
Forked from pocper/nycu-soc-fp
soc lab final project
Verilog 3
ic contest 2019 ~ 2024 ็ ็ฉถๆๅ่ณฝใๆฑบ่ณฝ้ก็ฎๆด็
