Skip to content

Fix DMA for framed packed mode #3

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
bvernoux merged 1 commit into from
Aug 20, 2025
Merged

Fix DMA for framed packed mode #3

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
34 changes: 24 additions & 10 deletions m4/adchs.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -88,16 +88,30 @@ void ADCHS_DMA_init(uint32_t dest_addr, uint8_t packed)
/* Modulo with round rubin last LLI point to First in infinite loop */
adchs_dma_lli[i].next_lli = (uint32_t)(&adchs_dma_lli[(i+1)%ADCHS_DMA_NUM_LLI]);

adchs_dma_lli[i].control = ( (nb_dma_transfer) << 0) |
(0x2 << 12) |
(0x2 << 15) |
(0x2 << 18) |
(0x2 << 21) |
(0x1 << 24) |
(0x1 << 25) |
(0x0 << 26) |
(0x1 << 27) |
(0x0UL << 31);
if (packed==HYDRASDR_PACKING_TIMESTAMP_ON) {
adchs_dma_lli[i].dst_addr+=4; // have to skip the packet header
adchs_dma_lli[i].control = ( (nb_dma_transfer-1) << 0) |
(0x2 << 12) |
(0x1 << 15) | // 4x burst because of offset
(0x2 << 18) |
(0x2 << 21) |
(0x1 << 24) |
(0x1 << 25) |
(0x0 << 26) |
(0x1 << 27) |
(0x0UL << 31);
} else {
adchs_dma_lli[i].control = ( (nb_dma_transfer) << 0) |
(0x2 << 12) |
(0x2 << 15) |
(0x2 << 18) |
(0x2 << 21) |
(0x1 << 24) |
(0x1 << 25) |
(0x0 << 26) |
(0x1 << 27) |
(0x0UL << 31);
}
}

if(packed)
Expand Down