Add end-to-end profiling instrumentation to CUDA IPC store path

[Copilot]

Adds time.perf_counter() timing to the CUDA IPC (handle-based) store path to expose per-stage latency for both the vLLM forward thread and the GPU transfer server.

HandleTransferContext.submit_store() — [FWD-IPC] log

Times each step on the forward thread (the path that blocks vLLM):

• event.ipc_handle() serialization
• _send_request() MQ round-trip
• .to_cuda_future() conversion

[FWD-IPC] req=cmpl-xxx ipc_handle=0.012 send_request=0.841 to_cuda_future=0.203 total=1.056 ms

GPUTransferModule.store() — [GPU-STORE] + [GPU-STORE-CHUNK] logs

Breaks down every stage in the server-side store:

• resolve_obj_keys, copy_view_block_ids_to_gpu
• Event.from_ipc_handle + vllm_event.wait
• event_bus.publish / publish_on_stream
• reserve_write
• Per-chunk kernel launch (multi_layer_block_kv_transfer) and lmcache_memcpy_async_d2h
• event.record() and submit_callback_to_stream

[GPU-STORE] req=cmpl-xxx resolve_keys=0.021 copy_block_ids=0.314 event_ipc_wait=0.182 event_publish=0.095 reserve_write=0.412 kernel_loop=48.231 event_record=0.031 submit_cb=2.104 total=51.390 ms (num_chunks=2, num_groups=1)
[GPU-STORE-CHUNK] req=cmpl-xxx chunk_idx=0 kernel=24.103 memcpy_d2h=0.041 ms
[GPU-STORE-CHUNK] req=cmpl-xxx chunk_idx=1 kernel=24.128 memcpy_d2h=0.038 ms

All timing variables are initialized before the try block so edge cases (empty obj_keys, all chunks skipped) never produce a NameError. No functional logic changed.