[DO NOT MERGE] Bitwuzla inconsistencies across platforms bug

[gussmith23]

Generating data for bitwuzla/bitwuzla#171

Strategy:

• convert all tests to use Bitwuzla.
• Run them on my M3 macbook and on github's runners.
• See which tests differ.
• Generate SMT for those tests and send to bitwuzla.

[gussmith23]

These tests failed on my Mac:

  Lakeroad tests :: addmulor_3_stage_unsigneds_9_bit.v
  Lakeroad tests :: one_stage_add_mul_add_signed_11_bit_xilinx.sv
  Lakeroad tests :: one_stage_add_mul_add_signed_12_bit_xilinx.sv
  Lakeroad tests :: two_stage_mul_and_lattice.v
  Lakeroad tests :: xilinx-7-series/7_series_addmuladd_1_stage_signed_11_bit.sv
  Lakeroad tests :: xilinx-7-series/7_series_addmulsub_1_stage_unsigned_17_bit.sv
  Lakeroad tests :: xilinx-7-series/7_series_muladd_1_stage_unsigned_14_bit.sv
  Lakeroad tests :: xilinx-7-series/7_series_mulsub_1_stage_unsigned_14_bit.sv
  Lakeroad tests :: xilinx-7-series/7_series_mult_2_stage_unsigned_11_bit.sv
  Lakeroad tests :: xilinx-7-series/7_series_submulsub_2_stage_unsigned_18_bit.sv
  Lakeroad tests :: xilinx_muladd_0_stage_signed_8_bit_yosys_plugin.sv
  Lakeroad tests :: xilinx_muladd_0_stage_unsigned_13_bit.sv
  Lakeroad tests :: xilinx_mulsub_1_stage_unsigned_14_bit.sv
  Lakeroad tests :: xilinx_preaddmul_1_stage_signed_18_bit.sv
  Lakeroad tests :: xilinx_preaddmul_3_stage_signed_18_bit.sv
  Lakeroad tests :: xilinx_ultrascale_plus_mac_with_internal_shift.v

[gussmith23]

Tests that failed on GH runners:

  Lakeroad tests :: addmulor_3_stage_unsigneds_9_bit.v
  Lakeroad tests :: bsg_mul_add_unsigned/bsg_mul_add_unsigned_13bit.sv
  Lakeroad tests :: intel_cyclone10lp_mul_0_stage_unsigned_18_bit.v
  Lakeroad tests :: two_stage_multiplier_xilinx.v
  Lakeroad tests :: xilinx-7-series/7_series_muladd_1_stage_unsigned_14_bit.sv
  Lakeroad tests :: xilinx_muladd_0_stage_unsigned_13_bit.sv
  Lakeroad tests :: xilinx_mulsub_1_stage_unsigned_14_bit.sv
  Lakeroad tests :: xilinx_mult_1_stage_signed_11_bit.sv
  Lakeroad tests :: xilinx_mult_1_stage_unsigned_11_bit.sv
  Lakeroad tests :: xilinx_preaddmul_1_stage_signed_18_bit.sv
  Lakeroad tests :: xilinx_ultrascale_plus_mac_with_internal_shift.v

[vcanumalla]

My instinct tells me we should merge this @ninehusky .

[ninehusky]

I have moved on from this project, and thus have no basis to judge the ideal path forward. Cheers.

AC