Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
As was reported in testing on real hardware on TLVC in Mellvik/TLVC#228 and Mellvik/TLVC#229, the 16550A and subsequent UARTs require special handling of the interrupt enable register, unless the FIFO is completely read during each interrupt received.
This is because the 16650 uses level-active interrupt signaling while the 8259 PIC is configured for edge-triggered interrupt detection. Reading all the bytes from the UART receive data register per interrupt ensures that the next byte received causes an edge transition on the interrupt pin of the 16550, which fixes the UART hang bug seen.
Thanks @Mellvik for the identification and testing of this problem!