Analog CMOS IC Design and Simulation Using Electric VLSI Tool 🔌

📌 Overview

This repository contains the design, layout, and simulation fundamental CMOS analog chips using the Electric VLSI EDA Tool and LTspice. The project focuses on essential CMOS building blocks commonly used in analog and digital IC design, including transistor-level schematic creation, layout implementation, and SPICE-based simulation.

🚀 Tools Used

• Electric VLSI EDA Tool (electricBinaryFull-9.08)
• Eclipse Temurin
• LTspice

🔧 CMOS Analog Circuit Projects

• PMOS Transistor
• NMOS Transistor
• CMOS Inverter
• Common Source Amplifier
• Common Drain Amplifier
• Ring Oscillator

Each project may include:

• Schematic designs
• IC layouts
• SPICE netlists
• Simulation files
• Waveform outputs

🔗 Circuit Layouts & Netlists

PMOS Transistor

Fig. 1 PMOS Schematic and Layout

• DC Sweep Analysis
  In LTspice, open the generated netlist (pmos/pmos.spi) and plot the following traces:
  
  • Id(Mpmos_1) upper pane
    
  • Is(Mpmos_1) lower pane

  vs s 0 DC 0
  vb b 0 DC 0
  vg g 0 DC 0
  vd d 0 DC 0
  .dc vd 0 -5 -1m vg 0 -5 -1
  .include "C:\C5_models.txt"
  

---

NMOS Transistor

Fig. 2 NMOS Schematic and Layout

• DC Sweep Analysis
  In LTspice, open the generated netlist (nmos/nmos.spi) and plot the following traces:
  
  • Id(Mnmos_0) upper pane
    
  • Is(Mnmos_0) lower pane

  vs s 0 DC 0
  vb b 0 DC 0
  vg g 0 DC 0
  vd d 0 DC 0
  .dc vd 0 5 1m vg 0 5 1
  .include "C:\C5_models.txt"
  

---

CMOS Inverter

Fig. 3 CMOS Inverter Schematic and Layout

• DC Sweep Analysis
  In LTspice, open the generated netlist (cmos-inverter/cmos-inverter-dc.spi) and plot the following traces:
  

  • V(vin) upper pane
    
  • V(vout) lower pane

  vdd vdd 0 DC 5
  vgnd gnd 0 DC 0
  vin vin 0 pulse (0 5 0 1n 1n 20n)
  .include "C:\C5_models.txt"
  .dc vin 0 5 1m
  

• Transient Analysis
  In LTspice, open the generated netlist (cmos-inverter/cmos-inverter-tran.spi) and plot the following traces:
  

  • V(vin) upper pane
    
  • V(vout) lower pane

  vdd vdd 0 DC 5
  vgnd gnd 0 DC 0
  vin vin 0 pulse (0 5 0 1n 1n 10n 20n)
  .include "C:\C5_models.txt"
  .tran 1n 100n
  

---

Common Source Amplifier

Fig. 4 Common Source Amplifier Schematic and Layout

• DC Analysis
  In LTspice, open the generated netlist (common-source-amplifier\common-source-amp-dc.spi) and plot both traces:
  

  • V(vin)
    
  • V(vout)

  vdd vdd 0 DC 5
  vin vin 0 dc 5
  .dc vin 0 5 .1
  .include "C:\C5_models.txt"
  

• Transient Analysis
  In LTspice, open the generated netlist (common-source-amplifier\common-source-amp-tran.spi) and plot the following traces:
  

  • V(vin) upper pane
    
  • V(vout) lower pane

  vdd vdd 0 DC 5
  vin vin 0 sin(0.9 0.005 1k 0 0 0 50)
  .tran 0 5m
  .include "C:\C5_models.txt"
  

• AC Analysis
  In LTspice, open the generated netlist (common-source-amplifier\common-source-amp-ac.spi) and plot the following traces:
  

  • V(vin) upper pane
    
  • V(vout) lower pane

  vdd vdd 0 DC 5
  vin vin 0 DC 0.9 AC 1
  .ac dec 100 100 10g
  .include "C:\C5_models.txt"
  

---

Common Drain Amplifier

Fig. 5 Common Drain Amplifier Schematic and Layout

• DC Analysis
  In LTspice, open the generated netlist (common-drain-amplifier\common-drain-amp-dc.spi) and plot both traces:
  

  • V(vin)
    
  • V(vout)

  vdd vdd 0 DC 5
  vb vb 0 DC 1
  vin vin 0 dc 5
  .dc vin 0 5 .1
  .include "C:\C5_models.txt"
  

• Transient Analysis
  In LTspice, open the generated netlist (common-drain-amplifier\common-drain-amp-tran.spi) and plot the following traces:
  

  • V(vin) upper pane
    
  • V(vout) lower pane

  vdd vdd 0 DC 5
  vb vb 0 DC 1
  vin vin 0 sin(4 1 1k 0 0 0 50)
  .tran 0 5m
  .include "C:\C5_models.txt"
  

• AC Analysis
  In LTspice, open the generated netlist (common-drain-amplifier\common-drain-amp-ac.spi) and plot the following traces:
  

  • V(vin) upper pane
    
  • V(vout) lower pane

  vdd vdd 0 DC 5
  vb vb 0 DC 1
  vin vin 0 DC 4 AC 1 SIN(4 1 1k 0 0 0 50)
  .ac dec 100 100 10g
  .include "C:\C5_models.txt"
  

---

Three Stage Oscillator

Fig. 6 Common Drain Amplifier Schematic and Layout

• Transient Analysis
  In LTspice, open the generated netlist (ring-oscillator\ring-oscillator.spi) and plot the following trace:
  

  • V(osc_out)
    

  vdd vdd 0 DC 5
  .tran 0 30n
  .include "C:\C5_models.txt"
  

  Note: Before running the SPICE simulation, all SPICE code in the CMOS inverter schematic and layout should be removed or converted into * comments.

---