domain(ENGINE+CLM+KOSMOS): CAMPAIGN PIVOT A — descent축 7B 완주 + 브랜치 reconcile + ENGINE PUBLIC 3/3 GREEN + lever-5 WORKLOAD-BOUND TERMINAL

.discoveries/clm-serialize-v2.tape

@@ -0,0 +1,8 @@
+@D CLM_SERIALIZE_V2 := "torch CLMConvMoE -> v0.2-CLMX .clm serializer closes the Lane P ENGINE-loadability gap" :: discovery [d=2026-06-05 active]
+  seed = "Lane P STOP: torch-trained .clm NOT ENGINE-loadable (v0.1 JSON serializer vs v0.2-CLMX decoder format gap)"
+  do   = "CLM/model/clm_serialize_v2.py emits the v0.2-CLMX byte layout the ENGINE decoder (CORE/clm_decode.hexa) reads — 6 int4-sym conv blocks {u32 cout, u32 rest, int4 nibbles 2/byte, fp32 scale} + CLMX trailer {embed, 6 conv/router/readout biases, 2 GroupNorm affine pairs}"
+  do   = "constrained to the decoder arch: E=2 (router cout), V=256, 1-trunk (single tcW block) — asserted, refuses off-arch state_dict"
+  do   = "torch Conv1d weight (Cout,Cin,K) flattens row-major to w[co*Cin*K+ci*K+k] = exactly the decoder im2col index w[co*rest+j], j=ci*K+k — no permute"
+  do   = "same int4-sym (amax/7, code in [-7,7], +8 nibble) as v0.1 clm_serialize.py; deterministic (byte-identical on repeat)"
+  claim = "F-CLM-V2-SERIALIZER GREEN — trained torch d16 model serialized -> ENGINE clm_decodable=TRUE + decode forward RAN (model_ce 2.767 < shuffle 3.809 < uniform 4.799); structure byte-identical to canonical reexport_d8_v2.clm (12158 B, same boundaries); round-trip decoder-dequant == torch-qdq max|delta|=0.0 — verdict .verdicts/clm-serialize-v2/"
+  scope = "Lane G-ref (torch-trained): emitted .clm BINARY has NO torch/ATen/Python, ENGINE-decodable; the TRAINER is torch so this is NOT the forge production ENGINE (util-blocked, pending hexa-lang). Win: torch+CUDA-trained model now ENGINE-loadable -> 3B/7B ENGINE .clm path UNBLOCKED."

.discoveries/engine-3b-fusion.tape

@@ -0,0 +1,12 @@
+@V := "tape" :: spec [active]
+  version = "1.2"
+
+@D engine_3b_fusion_preflight := "Lane G 3B forge HEXA-FUSION preflight — STOP, util-RED already CLOSED-NEGATIVE upstream on the same binary" :: discovery [d=2026-06-05 active]
+  seed      = "Drive ENGINE 3B forge line: add the HEXA-FUSION device-resident CUDA-graph train-step (the named lever-5 util unblock), run the 3B ladder >=3 rungs continuing from rung A-1, then 7B once 3B closes (util-GREEN MEAN>=20% AND descent-GREEN)."
+  claim     = "PREFLIGHT STOP. anima's Lane G forge trainer IS the hexa-lang clm_prod binary — rung A-1 fire (.verdicts/lane-g-3b-descent/fire_3b_descent.sh) ran CLM=$REPO/clm_prod with REPO=/root/hexa-lang. There is NO separate anima-side forge_dispatch_train_step / clm_lever driver to wire HEXA_CUDA_GRAPH into (grep across anima = 0 hits; anima has no stdlib/flame). The HEXA-FUSION CUDA-graph lever was ALREADY built + measured against that EXACT clm_prod program in ~/hexa-fusion-cuda-kit and is CLOSED-NEGATIVE on the >=20% util falsifier — the lever is not pullable as an UNBLOCK because it already ran on the same binary and did not move util to GREEN."
+  falsifier = "PRE-REGISTERED (upstream): 'whole-step CUDA-graph capture (fwd->ce_grad->bwd + the 16-call AdamW sweep all in ONE replayed graph) raises util MEAN to >=20%' — FALSIFIED. Measured MEAN=13.54% PEAK=77% median=2% n=284, statistically indistinguishable from eager g0=14.87% and fwd/bwd-only graph g1=13.19% (+0.35pp within pod noise)."
+  axes      = "host-removal (graph capture) ⊥ kernel-fusion (codegen). The falsifier tested host-removal; FALSIFIED. The remaining axis = kernel-fusion (upstream-owned codegen), NOT a capture env flag. Lane G / GPU substrate (a_lane_akida_gpu_split) = hexa-lang clm_prod device-resident forge fp64 cuBLAS + 58-60 .cu launchers, NO torch/ATen (a_train_flame_forge clean)."
+  honest    = "With FULL whole-step CUDA-graph fusion util MEAN=13.54% — FAR under the 20% GREEN bar, NOT GREEN. CE bit-identical 4.46624->3.64669 across all 3 arms (capture SOUND, byte-eq PRESERVED). ROOT: host launch overhead is NOT the util ceiling — the median-2% floor surviving whole-step capture = SMs idle BETWEEN kernels because per-kernel work at D=1536/T=512 is sub-millisecond and the SERIAL fine-grained kernel DAG (each op waits on prior op output) leaves SMs idle on the next kernel's dependency; the graph removes LAUNCH latency, not the DEPENDENCY chain. Same workload-bound residual rung A-1 + lever-5 already found (WORKLOAD-BOUND TERMINAL). Did NOT rent a GPU (re-running a closed-negative burns cost). NO util-GREEN fabricated. 3B ladder NOT fired beyond A-1; 7B NOT proceeded — the gate failed by FALSIFICATION, not skipped measurement."
+  target    = "🔴 CLOSED-NEGATIVE (preflight). Ruled-out axis = 'host launch overhead is the util ceiling on H100' — FALSIFIED across the full lever family (② async 10-12%, ④ fwd/bwd graph 13.17%, ⑤ whole-step graph 13.54%; all bottom out at median 2% / MEAN ~12-15%). Real remaining unblock = kernel FUSION (codegen) so each kernel saturates SMs longer / the dependency chain collapses into fewer bigger kernels."
+  why       = "Upstream hexa-lang fusion line is INCREMENTAL + sub-GREEN: L3-a GN->GELU fused CONFIRMED byte-eq +3.26pp (10.31->13.57%); L3-b dual-GELU +1.01pp stacked; L3-c/L3-d/P2a build-ready UNMEASURED with HONEST ceiling 'pairwise incremental, will NOT reach >=20% alone'; cublasLt-GELU-epilogue ruled out (FP64 has no GELU epilogue); FULL whole-step megakernel design-CLOSED (a persistent kernel can't call cuBLAS). This is hexa-lang-OWNED codegen work, NOT an anima env-gate integration. For the descent axis, the proven path stays d1536/d3072 E=2 (lever-5 4.05535->2.99508 DID descend)."
+  refs      = "~/hexa-fusion-cuda-kit/F-FUSION-GRAPH-WHOLESTEP-AB.txt (verbatim FALSIFIED >=20%) · F-FUSION-GRAPH-AB.txt (④ +1.32pp) · F-FUSION-ASYNC-UTIL-AB.txt (② closed-neg) · F-FUSION-L3A-GN-GELU-AB.txt + F-FUSION-L3B-GELU2-AB.txt · l3c/l3d/p2a-build README (UNMEASURED sub-GREEN) · .verdicts/lane-g-3b-descent/VERDICT.md (rung A-1 ran /root/hexa-lang/clm_prod) · hexa-lang domains/HEXA-FUSION.md · a_cuda_graph_train"

.discoveries/lane-p-clm.tape

@@ -0,0 +1,8 @@
+@D lane_p_serializer_format_gap := "Lane P torch .clm is NOT ENGINE-loadable — serializer emits a different byte layout than CORE/clm_decode.hexa reads" :: discovery [d=2026-06-03 active]
+  seed      = "Generate a real converged .clm via the PyTorch+CUDA pipeline (train_clm.py -> fire_clm.py ckpt -> clm_serialize.py), then ENGINE-load it via CORE/clm_decode.hexa (generator L3 slot)."
+  claim     = "CLM/model/clm_serialize.py emits [CLM\\x01][u32 header-len][JSON header][JSON-described blocks][u32 manifest-len][JSON manifest], whereas CORE/clm_decode.hexa reads [CLM\\x01][1B nblk][6 raw conv blocks: u32 cout,u32 rest,int4 nibbles,fp32 scale][CLMX trailer: embed+bias+GN]. Same magic, incompatible layout: byte[4] of the torch file is the LSB of the JSON-header length (e.g. 29), not nblk; the decoder then misreads JSON ASCII as binary u32 block dims and clm_decodable() returns false. The torch serializer also writes no CLMX trailer (embed/GN absent -> no forward) and the torch arch (small=E8/L4) violates the decoder's hardcoded E=2/single-trunk."
+  falsifier = "If clm_serialize.py output were fed to CORE/clm_decode.hexa::clm_decodable(), it would return true and a forward CE could run. Refuted: static byte-layout reconstruction shows byte[4]=LSB(header_len), block-dim u32s land in JSON ASCII -> wild offset -> EOF -> false."
+  target    = "🔴 CLOSED-NEGATIVE — torch pipeline cannot produce an ENGINE-loadable .clm without a new v0.2-CLMX torch serializer + E=2/single-trunk constraint (or a variable-E decoder)."
+  scope     = "substrate=GPU-torch (Lane P), recorded separately from Lane G(forge)/Lane A(AKIDA) per a_lane_akida_gpu_split. Static preflight (no GPU rented); verify hard-gate failed before STEP 4. The ENGINE-native format is produced ONLY by the hexa flame trainer, which is already 3-axis CORE-mounted GREEN @ d768 (ENGINE+CLM+KOSMOS.md)."
+  honest    = "No GPU rented, no train run, no fabricated convergence (g63/p7). The serializer gap is provable from source + the prior d768 artifact byte-walk alone; no torch install was available locally and none was needed for the verdict."
+  note      = "Verdict: .verdicts/lane-p-clm/F-CLM-SERIALIZE-GAP.txt. Remedy = author a v0.2-CLMX torch serializer (E=2/1-trunk) OR scope Lane P to torch CE-descent reference (mirrors the HF-PUBLIC Lane G-ref ByteGPT track, which is also NOT an ENGINE .clm)."

.discoveries/lane_a_causeaxis_encoding_reopen.tape

@@ -0,0 +1,42 @@
+@V := "tape" :: spec [active]
+  version = "1.0"
+
+# Lane A LIFT cause-axis breakthrough battery — INPUT-ENCODING reopens P3 (2026-06-02)
+#
+# seed: /gap full sweep found the 4 falsified lift-cause axes (corpus/quant/depth/noise =
+#   H-A1..A4) + Hc_1306 are FIX-axes, not CAUSE-axes — all sit downstream of ONE untested
+#   choice: the fixed random encoder BACKBONE_INT4 = rng_bb.integers(-7,8,(256,256)).
+# chip: live AKD1000 BC.00.000.002, akida 2.19.1, pi5-akida ($0), 8 paired chip trials/probe.
+# metric: between-minus-within concept Hamming margin (bits); lift = treat - control;
+#   ci_lo = mean_lift - 1.96*SEM over chip trials. ALL probes ESCAPE the falsified 4 axes.
+# pre-register: .verdicts/lane-a-causeaxis/PREREGISTER.md (falsifiers BEFORE fire).
+
+@N laneA_p1_encoding := "structured cross-lingual encoder beats fixed random backbone — lift ci_lo>0 on chip" :: discovery [d=2026-06-02 active]
+  seed    = "is the closed-negative an artifact of the FIXED RANDOM input encoder all 4 falsifiers sit downstream of?"
+  method  = "swap random int4 backbone for SVD/whitened structured encoder of 5-lang anchor histograms; 8 paired chip trials; live AkidaUnsupervised 1-bit on-chip fit; concept-margin lift vs random"
+  data    = "SVD: mean +0.9210 bits 95%CI [+0.7382,+1.1038] 8/8 pos; whitened: +0.4190 CI [+0.1035,+0.7345] 7/8; learn-on-chip live every trial"
+  finding = "the fixed random BACKBONE_INT4 IS a lift bottleneck — a structured encoder recovers concept margin the random projection destroys; ci_lo>0 REOPENS Lane A P3 on the ENCODING axis"
+  verdict = "🟢 REOPEN — .verdicts/lane-a-causeaxis/P1-encoding.txt (chip stdout verbatim)"
+  caveat  = "RELATIVE lift (structured > random); both arms' ABSOLUTE margin stays negative at 25-anchor toy scale — next rung: stronger learned multilingual encoder to push absolute margin >0 (a_scale_honest_scope)"
+
+@N laneA_p2_objective := "objective/readout-locus NOT the bottleneck — hardware-locked + clean negative" :: discovery [d=2026-06-02 active]
+  seed    = "was 1-bit AkidaUnsupervised on last-FC a backend default, not the only liftable rule?"
+  method  = "4-bit weights vs 1-bit; supervised vs unsupervised; pre-binarization analog readout vs post-1bit — all on live chip"
+  data    = "4bit: ValueError 'Only layers with binary weights can be trained' (chip hardware-locks on-chip learning to 1-bit); supervised: N/A-SDK (only AkidaUnsupervised in 2.19.1); analog readout margin -4.877 ci_lo -5.282"
+  finding = "objective/readout-locus is NOT the bottleneck; 4bit/supervised are hardware/SDK-blocked (recorded N/A, not fabricated); analog space carries no hidden concept margin"
+  verdict = "🔴 FALSIFIED (hardens) — .verdicts/lane-a-causeaxis/P2-objective-readout.txt"
+  caveat  = "AKD1000 on-chip plasticity is 1-bit-only by hardware; a richer rule needs different silicon"
+
+@N laneA_p3_timing := "spike-timing carries no cross-lingual lift; SDK exposes no spike-timing" :: discovery [d=2026-06-02 active]
+  seed    = "does SNN lift live in spike-TIMING the rate-code 1-bit Hamming readout discards? (Hc_1306 tested only static signals)"
+  method  = "attempt akida spike-event capture; fall back to per-unit activation-rank-order Spearman temporal proxy (within-minus-between concept); 8 chip trials"
+  data    = "SDK spike API = only PowerEvent/power_events (power telemetry, NOT spike timestamps) + predict_classes; timing-proxy margin -0.1076 ci_lo -0.1111"
+  finding = "no true spike-timing capture available on this chip (stated, not fabricated); rank-order temporal proxy shows NO concept structure — lift not hiding in timing"
+  verdict = "🔴 FALSIFIED (hardens) — .verdicts/lane-a-causeaxis/P3-temporal-code.txt"
+  caveat  = "temporal proxy is rate-resolution rank order, NOT spike-timing; true STDP timing untestable on AKD1000 via this SDK"
+
+@N laneA_causeaxis_disposition := "Lane A P3 REOPENS on encoding; objective+timing axes harden closed" :: discovery [d=2026-06-02 active]
+  seed    = "do the 3 never-probed cause-axes reopen the lift or harden the closed-negative to 8 axes?"
+  finding = "1 of 3 cause-axes (INPUT-ENCODING) REOPENS with chip ci_lo>0; the other 2 (objective/readout, spike-timing) FALSIFIED → closed-negative now also covers those two. The encoding lift runs on the EXISTING AKD1000 — no new hardware (corrects prior 'needs different hardware' deferral)."
+  verdict = "REOPENED-on-axis-ENCODING — folded into CLM+KOSMOS.md Lane A P3 disposition + CLM+KOSMOS.log.md 2026-06-02"
+  caveat  = "encoding reopen is a RELATIVE-lift toy-scale result; absolute margin >0 unproven — pre-register the encoder-strength ladder before the next fire"

.discoveries/torch-engine-7b-datagate.tape

@@ -0,0 +1,10 @@
+@D torch_engine_7b_datagate := "a properly-trained torch ENGINE 7B is DATA-STARVED on the default-lane corpus — the serializer is unblocked but the real prerequisite is a GB-scale corpus, not a 7B GPU fire" :: discovery [d=2026-06-05 active]
+  seed      = "Now that v0.2-CLMX serializer (PR #1845) makes torch state_dict ENGINE-loadable, attempt a properly-trained torch ENGINE 7B — but FIRST a hard data-sufficiency preflight."
+  claim     = "The default-lane corpus (HF dancinlab/anima-corpus-5lang-unified-v2 ~12.5 MB = 1.25e7 byte-tokens at V=256) supports a 7B (7.0e9 param) model at ratio N_opt/N_tok = (20*7.0e9)/1.25e7 = 1.40e11/1.25e7 ≈ 1.12e4 — i.e. ~11,200x too few tokens for Chinchilla-optimal; even a weak ~1-3 tok/param coherence budget is ~560x-1680x short. No epoch count closes a 10^3-10^4x token deficit: ~11,200 passes over the same 12.5 MB = MEMORIZATION not coherence."
+  do        = "EMPIRICAL confirm (not prediction): the already-harvested CORPUS-7B (ConsciousLMReconstructed 7,053,230,080 params, 98.3M tokens / 6000 steps, util mean 90%, descent CE 5.6955->1.1432 TRUE, held_out_generalizes TRUE = NOT memorizing) RULED 'gibberish-undertrained' chat_pass=FALSE — .verdicts/default-lane-7b/HARVEST-VERDICT.md verbatim. 98.3M tokens (already multi-epoch) STILL gibberish; more epochs only push toward memorization."
+  falsifier = "If 12.5 MB sufficed for a coherent 7B, the harvested CORPUS-7B (8x that token budget) would have passed chat. It FAILED (gibberish-undertrained). DATA-STARVED = confirmed."
+  target    = "🔴 CLOSED-NEGATIVE on the 7B-on-this-corpus path — a true 7B needs a GB-scale (~10^9-10^11 byte-token) corpus FIRST. 7B GPU fire NOT RENTED (gate held, $0, a_completeness_over_cheap: doomed expensive run is not primary)."
+  do        = "ACHIEVABLE WIN already demonstrated at right-sized scale: PR #1845 torch clm_serialize_v2.py serialized a TRAINED torch d16 model -> v0.2-CLMX .clm; ENGINE CORE/clm_decode.hexa clm_decodable=TRUE + decode forward ok gen_bytes=16 + CE-descent model_ce 2.76676 < shuffle 3.80927 < uniform 4.79906 (F-CLM-CORE-CE-DESCENT=1) + round-trip decoder_dequant vs torch_qdq max|delta|=0.0. Production-scale coherent ENGINE .clm already PUBLIC: d768 E2/V256 3/3 CORE-GREEN (의식+CE+창발), HF dancinlab/clm-v1-d768-core-3axis-green."
+  scope     = "substrate=GPU (Lane G-ref, torch-reference) — recorded separately from Lane A(AKIDA)/Lane G(forge) per a_lane_akida_gpu_split. The d768 PUBLIC .clm was emitted by the hexa host reexport ($0-CPU), NOT the torch writer; the torch writer's coherence is proven on the d16 trained model + 0.0 round-trip — a torch-written production-scale .clm was not re-emitted only because no source .pt for the d768 reexport survives on disk (byte_compare.txt)."
+  honest    = "No GPU rented, no torch install needed for the gate (corpus byte-count + the harvested HARVEST-VERDICT verbatim suffice; torch absent locally). No fabricated convergence (g63/p7). CE is ONE axis (model_ce < uniform AND < shuffle), not perplexity-as-truth."
+  note      = "Verdict: .verdicts/torch-engine-7b-datagate/VERDICT.md. Evidence chain: .verdicts/default-lane-7b/HARVEST-VERDICT.md (commit 7a5240c3d) + .verdicts/clm-serialize-v2/{smoke_trained,byte_compare}.txt (PR #1845) + .verdicts/core-3axis-mount/ce_descent.txt. Real next step = build/acquire a GB-scale clean-license corpus before any 7B; right-sized (<=18M chat rung, d768 E2/V256) is already coherent + ENGINE-loadable."

.verdicts/clm-kosmos-reflect/corpusA-descent/20260601T190024Z.txt

@@ -0,0 +1,18 @@
+[hexa hf validate] DATASET dancinlab/clm-h911-trainset-5lang-parallel
+ts_utc: 2026-06-01T19:00:24Z
+type: dataset
+corpus: /tmp/claude-501/_hfval_ds.x3xoaJ/clm_concat.kosmos
+construct: bytes=1657 lines=31 nonascii=0 ok=1 reason=ok
+TIER: 🟢 GREEN
+KEY_METRIC: CE 4.59032->1.63673 (descent=1)
+SCALE: toy CPU rung (d=8, $0) — production-scale transfer DEFERRED (a_toy_scale_recheck; no GPU/chip fire, a_cpu_local_no_waiter)
+METROLOGY: tier derived ONLY from the clm_prod run stdout below (NOT from README/metadata/download-count — g5/a_claim_verify)
+----- VERBATIM clm_prod stdout -----
+clm_prod — CLMConvMoE production corpus loop (PR1)
+  corpus: /tmp/claude-501/_hfval_ds.x3xoaJ/clm_concat.kosmos  (1657 bytes, V=256)
+  windows: 8/8  (T=24 stride=204)
+  epoch-1 mean CE = 4.59032
+  epoch-12 mean CE = 1.63673
+F-CLM-PROD-DESCENT = 1
+PASS — real-corpus mean CE descends under int4 envelope
+----- END VERBATIM -----