🎓 ECE Undergraduate @ NIT Silchar | 🧠 GATE Aspirant
💡 Aspiring VLSI Engineer | 📘 Documenting my journey with GitHub

• 🎓 I'm currently a final year Electronics & Communication Engineering student at NIT Silchar
• 💻 Exploring the core domain: VLSI, Digital Design, RTL, FPGA
• 🔬 Currently building hands-on projects in Verilog
• 🧠 Preparing for GATE (ECE) while developing my tech portfolio

A 32-bit Single-Cycle RISC-V (RV32I) processor implemented in Verilog HDL, featuring a modular RTL architecture, instruction fetch/decode/execute datapath, control unit, register file, ALU, data memory, and functional simulation using Xilinx Vivado.

A 32-bit Direct-Mapped Cache Controller implemented in Verilog HDL, featuring cache hit/miss detection, tag comparison, valid-bit management, FSM-based cache control, cache refill logic, and behavioral main memory simulation in Xilinx Vivado.

A simplified AMBA AXI4 Memory Controller implemented in Verilog HDL, featuring AXI4-compliant read/write channels, independent Read and Write FSMs, burst transaction support, memory interface logic, and simulation-based verification using Xilinx Vivado.

A growing collection of Verilog HDL, RTL Design, Computer Architecture, FPGA, and VLSI projects developed as part of my digital hardware design and verification journey.

• 🚀 Advanced RTL Design using Verilog HDL
• 🚀 RISC-V Processor Design and Computer Architecture
• 🚀 VLSI Design Flow and CMOS Fabrication
• 🚀 FPGA Design using Xilinx Vivado
• 🚀 Embedded Systems and Microcontroller Programming
• 🚀 GATE ECE Preparation (Digital Electronics, Control Systems, Signal Processing, VLSI)

• 📧 Email: architaroy.1504@gmail.com
• 💼 LinkedIn: Archita Roy

🌱 This GitHub profile is my learning diary as I explore the intersection of theory and implementation in VLSI.