verilog_class_exercises

Class exercises for the course CAD with HDL

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
binaries		binaries
.gitattributes		.gitattributes
.gitignore		.gitignore
FA.v		FA.v
FA.vwf		FA.vwf
FA_B.v		FA_B.v
FA_B.vwf		FA_B.vwf
HA.v		HA.v
HA.vwf		HA.vwf
HEX7segDEC.v		HEX7segDEC.v
LICENSE		LICENSE
OR2_v1.v		OR2_v1.v
RAM1.v		RAM1.v
README.md		README.md
REGFILE1.v		REGFILE1.v
SUM2.v		SUM2.v
SUM2.vwf		SUM2.vwf
adder16.v		adder16.v
adder16.vwf		adder16.vwf
dec2to4_v1.v		dec2to4_v1.v
decoder_2_4.v		decoder_2_4.v
decoder_2_4.vwf		decoder_2_4.vwf
decoder_2_4_B.v		decoder_2_4_B.v
decoder_2_4_B.vwf		decoder_2_4_B.vwf
decoder_3_8_B.v		decoder_3_8_B.v
decoder_3_8_B.vwf		decoder_3_8_B.vwf
fulladder.v		fulladder.v
fulladder.vwf		fulladder.vwf
priority_encoder.v		priority_encoder.v
priority_encoder.vwf		priority_encoder.vwf
verilog_class_exercises.qpf		verilog_class_exercises.qpf
verilog_class_exercises.qsf		verilog_class_exercises.qsf

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