Command Line Arguments

Command line arguments are used when we want to avoid test bench recompilation. As the name suggests, we can give values to the program mentioning in the command line. The arguments passed in the command line are accessible in our SV code with the help of system functions called plusargs.

Plusargs

$test$plusargs

This function is used when there is a need to get some instruction from command line precisely a string to perform next lines of code.

It is to be noted that all characters of the string mentioned in the function should match the plusarg we provide after + in the command line. When the string matches, the function $test$plusargs returns 1 otherwise it returns 0.

Syntax:

$test$plusargs("string")

Simulation command:

vsim module_name -c -do "run -all;quit" +string

Note: We are using Mentor Questa simulator in Command Line Interface which explains the above command format.

Code Snippet 1

module CLI_testargs;
bit x;
initial begin:BEGIN-I
  x=$test$plusargs("START");
  $display("$test$plusargs returns %d",x);
  if(x)
    $display("Start process");
  else
    $display("exit");
end:BEGIN-I
endmodule

Simulation command:

vsim CLI_testargs -c -do "run -all;quit" +START

-> In the above code snippet, if we give START in the CL then we'll get x=1 and Start process is displayed.

OUTPUT

$test$plusargs returns 1  
Start process

GitHub code link: https://github.com/VINUTHNA-SRI/SystemVerilog_Course/blob/b7_Team_BJT/Misc_constructs/Command_Line_Arguments/CLI_testargs.sv
GitHub output link: https://github.com/VINUTHNA-SRI/SystemVerilog_Course/blob/b7_Team_BJT/Misc_constructs/Command_Line_Arguments/CLI_testargs.log

->The below code makes the usage of $test$plusargs in parallel execution of initial blocks.

Code Snippet 2

initial begin:BEGIN_I
  x=$test$plusargs("START");
  $display("@%0dns In first begin block",$time);
  $display("@%0dns $test$plusargs returns %d",$time,x);
  if(x)
    $display("@%0dns Start process",$time);
  else
    $display("@%0dns exit",$time);
end:BEGIN_I

initial begin:BEGIN_II
  x=$test$plusargs("START");
  $display("@%0dns In second begin block",$time);
  $display("@%0dns $test$plusargs returns %d",$time,x);
  if(x)
    $display("@%0dns Start process",$time);
  else
    $display("@%0dns exit",$time);
end:BEGIN_II

Simulation command:

vsim CLI_testargs2 -c -do "run -all;quit" +START

OUTPUT

@0ns In first begin block
@0ns $test$plusargs returns 1
@0ns Start process
@0ns In second begin block
@0ns $test$plusargs returns 1
@0ns Start process

->Since the string START is available for both the blocks the functions returns 1 in both at the same timestamp.

GitHub code link: https://github.com/VINUTHNA-SRI/SystemVerilog_Course/blob/b7_Team_BJT/Misc_constructs/Command_Line_Arguments/CLI_testargs2.sv
GitHub output link: https://github.com/VINUTHNA-SRI/SystemVerilog_Course/blob/b7_Team_BJT/Misc_constructs/Command_Line_Arguments/CLI_testargs2.log

$value$plusarg

This function is used when we need to take an input value from user through command line which can be further used or modified in the code.

In the simulation (in command line) we should explicitly give the value as string=value which follows +.

Syntax:

$value$plusargs("string=format_specifier",variable_name)

Here, format_specifier can be %d, %s etc.
The value we give is stored in variable_name and is accessible in the code.

Simulation command:

vsim module_name -c -do "run -all;quit" +string=value

Code Snippet 1

module CLI_valargs;
bit x;
int y;
string message;
initial begin:BEGIN_I
  x=$value$plusargs("msg=%s",message);
  $display("$value$plusargs used above returns %0d",x);
  $display(message);
  void'($value$plusargs("value=%d",y));
  y+=1;
  $display("Incremeneted value of y:%0d",y);
end:BEGIN_I

endmodule

->In the above code we are trying to give two value arguments(one is a string and the other is an integer) in the command line.

Simulation command:

vsim CLI_valargs -c -do "run -all;quit" +msg=Hey! +value=2

OUTPUT

$value$plusargs used above returns 1
Hey!
Incremeneted value of y:3

GitHub code link: https://github.com/VINUTHNA-SRI/SystemVerilog_Course/blob/b7_Team_BJT/Misc_constructs/Command_Line_Arguments/CLI_valargs.sv
GitHub output link: https://github.com/VINUTHNA-SRI/SystemVerilog_Course/blob/b7_Team_BJT/Misc_constructs/Command_Line_Arguments/CLI_valargs.log

Code Snippet 2

module CLI_valargs1;
bit x;
string y;
string s;
int fd,f;
string message;
initial begin
  x=$value$plusargs("msg=%s",message);
  $display("$value$plusargs used above returns %0d",x);
  $display(message);
  void'($value$plusargs("file=%s",y));
  fd=$fopen(y,"r");
  $fgets(s,fd);
  $display(s);
  $fclose(fd);

  fd=$fopen(y,"a");
  $fdisplay(fd,"Hurray!");
  $fclose(fd);
end

endmodule

->Here, we are trying to add contents to a file which we get from command line.

                         Fig1. Contents of sample.txt before simulation of code  

Simulation command:

vsim CLI_valargs1 -l "CLI_valargs1.log" -c -do "run -all;quit" +msg=Hey! +file="sample.txt"

OUTPUT

$value$plusargs used above returns 1
Hey!
We are trying to open this file using command line argument and it worked!

                         Fig2. Contents of sample.txt after simulation of code 

GitHub code link: https://github.com/VINUTHNA-SRI/SystemVerilog_Course/blob/b7_Team_BJT/Misc_constructs/Command_Line_Arguments/CLI_valargs1.sv
GitHub output link: https://github.com/VINUTHNA-SRI/SystemVerilog_Course/blob/b7_Team_BJT/Misc_constructs/Command_Line_Arguments/CLI_valargs1.log

Note: Both the functions $test$plusargs and $value$plusargs are case sensitive.