PLC2's Release of more AXI4Lite-components#37
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stefanunrein wants to merge 5 commits intoVHDL:devfrom
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Co-authored-by: Srikanth Boppudi <Srikanth.Boppudi@plc2.de> Co-authored-by: Nimitha Mallikarjuna <> Co-authored-by: Adrian Weiland <Adrian.Weiland@plc2.de> Co-authored-by: Patrick Lehmann <Patrick.Lehmann@plc2.de> Co-authored-by: Asif Iqbal <Asif.Iqbal@plc2.de> Co-authored-by: Jonas Schreiner <jonas.schreiner@plc2.de>
# Conflicts: # .sigasi/project.sigasi # regression.tcl
made pipeline stageless, merge junit reports fix naming test simple pages job fix reset Oram adapter added Miktex job, enabled pages for NVC Edit AXI4Lite_Register_initial.vhdl added Sphinx job Co-authored-by: Patrick Lehmann <Patrick.Lehmann@plc2.de> Co-authored-by: Patrick Lehmann <Paebbels@gmail.com>
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New Features
axi4lite_HighResolutionClockaxi4lite_OCRAMAdapteraxi4lite_UARTaxi4lite_DRPBridgeChanges
.editorconfigis widely adopted.Documentation
Tests
CI