Add 39-bit virtual memory scheme support for riscv64.#49
Draft
Sakura286 wants to merge 1 commit intoSnaipe:masterfrom
Draft
Add 39-bit virtual memory scheme support for riscv64.#49Sakura286 wants to merge 1 commit intoSnaipe:masterfrom
Sakura286 wants to merge 1 commit intoSnaipe:masterfrom
Conversation
Fixed 'context.c' test failure on riscv64. See issue Snaipe#44. Only riscv64 arch is affected in this commit, but you can modify memory_addr_bits variable to support other memory schemes.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Fixed arena memory allocation faillure on riscv64, see issue #44 .
The allocation assumes 48bit address on linux, but most RISC-V machines use 39bit address by default currently. I tried to add 39bit scheme to
arena.cand set it to all riscv64 build.But it may not be a good choice to decide memory address mode at configuration time.
satpregister, which contains address scheme on riscv64, is unreadable in user mode./proc/cpuinfo/proc/sys/vm/pagemap/proc/config.gzcould provide the info. But they are not always available on every machine and in cross compilation.So I set this PR to WIP. I would be appreciated if anyone helps me.