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Shahid Shann edited this page Jan 24, 2024
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Welcome to the SystemVerilogCourse wiki!
Welcome to the SystemVerilogCourse wiki!
| Sr. No | Topic |
|---|---|
| 1. | Data Types |
| 2. | Array |
| 3. | Structure and Union |
| 4. | User defined |
| 5. | Operators |
| 6. | Control Flow |
| 7. | Function |
| 8. | Task |
| 9. | Loops |
| 10. | Schedular Schematic |
| 11. | Process |
| 12. | Fine Grain Process Control |
| 13. | Interface |
| 14. | Constrains |
| 15. | Classes and OOPs |
| 16. | Functional Coverage |
| 17. | Assertion |
| 18. | Interprocess Communication |
| 19. | Misc Constructs |
| 20. | Differences between macros and parameters |