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[WaveTransform][NFC] XFAIL 11 tests failing with "Dbg values not emitted in LDV" #2428

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[WaveTransform][NFC] XFAIL 11 tests failing with "Dbg values not emitted in LDV" #2428

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0b6eb00
XFAIL 11 tests failing with Dbg values not emitted in LDV
TejaX-Alaghari May 6, 2026
a2c1966
Enable LWT
TejaX-Alaghari May 7, 2026
96a35d3
Move the XFAIL lines to the top
TejaX-Alaghari May 7, 2026
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6 changes: 4 additions & 2 deletions llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
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@@ -1,8 +1,10 @@
; XFAIL: *
; RUN: opt %s -strip-debug -o %t.no_debug.ll -S
; RUN: llc -mcpu=gfx1250 < %s -filetype=obj -o %t.with_debug.o
; RUN: llc -mcpu=gfx1250 < %t.no_debug.ll -filetype=obj -o %t.no_debug.o
; RUN: llc -amdgpu-late-wave-transform=1 -mcpu=gfx1250 < %s -filetype=obj -o %t.with_debug.o
; RUN: llc -amdgpu-late-wave-transform=1 -mcpu=gfx1250 < %t.no_debug.ll -filetype=obj -o %t.no_debug.o
; RUN: llvm-strip %t.with_debug.o %t.no_debug.o
; RUN: cmp %t.with_debug.o %t.no_debug.o

; Ensure that compiling with and without debug generates identical code.
; Test that adjustSchedDependency does not count debug instructions in bundles.

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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AMDGPU/debug-value.ll
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@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s
; XFAIL: *
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false -amdgpu-codegenprepare-break-large-phis=0 < %s | FileCheck %s

%struct.wombat = type { [4 x i32], [4 x i32], [4 x i32] }

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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AMDGPU/debug-value2.ll
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false < %s | FileCheck %s
; XFAIL: *
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -experimental-debug-variable-locations=false < %s | FileCheck %s

%struct.ShapeData = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32, i64, <4 x float>, i32, i8, i8, i16, i32, i32 }

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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AMDGPU/ds-read2-write2-debug-info.ll
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; XFAIL: *
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=debugify < %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s
; RUN: opt -passes=debugify < %s | llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck %s

@lds = addrspace(3) global [512 x float] poison, align 4

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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
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; XFAIL: *
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck %s

; Don't crash.

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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
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@@ -1,6 +1,6 @@
; RUN: llc -O0 -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,NOOPT %s
; RUN: llc -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,OPT %s

; XFAIL: *
; RUN: llc -amdgpu-late-wave-transform=1 -O0 -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,NOOPT %s
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=GCN,OPT %s

; GCN-LABEL: {{^}}test_debug_value:
; NOOPT: .loc 1 1 42 prologue_end ; /tmp/test_debug_value.cl:1:42
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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AMDGPU/post-ra-soft-clause-dbg-info.ll
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@@ -1,5 +1,6 @@
; XFAIL: *
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -experimental-debug-variable-locations=false < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn -mcpu=gfx900 -mattr=+xnack -amdgpu-max-memory-clause=0 -experimental-debug-variable-locations=false < %s | FileCheck -enable-var-scope -check-prefix=GCN %s

; Test the behavior of the post-RA soft clause bundler in the presence
; of debug info. The debug info should not interfere with the
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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll
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@@ -1,5 +1,6 @@
; XFAIL: *
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s

define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef %dst.coerce, ptr addrspace(1) inreg noundef %src.coerce, i64 inreg noundef %nElts, i64 inreg noundef %redOpArg, i1 inreg noundef %redOpArgIsPtr) #0 !dbg !4 {
; GFX942-LABEL: preload_block_count_x:
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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
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@@ -1,5 +1,6 @@
; XFAIL: *
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -experimental-debug-variable-locations=false < %s | FileCheck %s
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -experimental-debug-variable-locations=false < %s | FileCheck %s

%struct.A = type { [100 x i32] }

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13 changes: 7 additions & 6 deletions llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
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@@ -1,12 +1,13 @@
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s
; XFAIL: *
; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck -check-prefixes=CHECK,GREEDY -implicit-check-not=error %s
; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,BASIC %s
; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=fast -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=CHECK,FAST %s
; RUN: opt -passes=debugify -o %t.bc %s
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-GREEDY %s
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-BASIC %s
; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=greedy -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-GREEDY %s
; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -stress-regalloc=1 -vgpr-regalloc=basic -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-BASIC %s

; FIXME: Asserts when using -O2 + -vgpr-regalloc=fast
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s
; RUN: not llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stress-regalloc=1 -O0 -filetype=null %t.bc 2>&1 | FileCheck -implicit-check-not=error -check-prefixes=DBGINFO-CHECK,DBGINFO-FAST %s

; TODO: Should we fix emitting multiple errors sometimes in basic and fast?

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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll
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@@ -1,4 +1,5 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -experimental-debug-variable-locations=false < %s | FileCheck -check-prefix=GCN %s
; XFAIL: *
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -experimental-debug-variable-locations=false < %s | FileCheck -check-prefix=GCN %s
; Make sure dbg_value reports something for argument registers when they are split into multiple registers

define hidden <4 x float> @split_v4f32_arg(<4 x float> returned %arg) local_unnamed_addr #0 !dbg !7 {
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