[Feat] Intranode Dispatch&Combine Kernel #522
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…lpers Introduce the FlyDSL-implemented intranode EP dispatch / combine kernel plus the FlyDSL Python-layer extensions it depends on, rebased on origin/main. Kernel (kernels/): * dispatch_combine_intranode_kernel.py 4-phase dispatch + 3+1-stage combine (P2P scatter / CrossDeviceBarrier / WarpAccum / weight accum). Supports bf16/fp8 transport, optional fp8-direct-cast Stage-3 bf16<->fp8, StdMoE atomic path, weight scatter pinned to the combine-kernel fabric, and the skip_stage1 fast-path for upstream fused GEMM2 epilogues (weight scatter implicitly enabled iff enable_weights=True; no separate keep_wts flag). * dispatch_combine_intranode_op.py Launcher / JIT cache, including the combine_no_stage1 variant. * tests/kernels/test_profiler_dispatch_combine.py Verify + bench harness (--mode verify/profile/bench, --chip gfx942/950). FlyDSL helper extensions (python/flydsl/): * expr/arith.py: divui, remui, zext_i64, select_by_index. * expr/vector.py: bitcast_i32_to_v2bf16, bitcast_v2bf16_to_i32. * expr/rocdl/__init__.py: ballot_i64, readlane. * compiler/ast_rewriter.py: stop treating method / attribute calls (e.g. ptr.store(...)) as variable assignments when collecting the scf.for / scf.if carried-set. Style: rewritten on FlyDSL high-level surface (Python operators, scf.if-from-Python-if, FlyDSL Vector API for accumulators). Low-level mlir scaffolding only kept where strictly required (ROCDL intrinsics, buffer_ops, raw-LLVM atomic / pointer helpers). Bug fixes folded in: * dispatch StdMoE Phase 4: use unsigned comparison for is_local. Verify (8 GPU, gfx942, bf16): * default bs=256/h=7168/k=8 -> ALL PASS * --enable-std-moe bs=512/h=7168/k=8 -> ALL PASS
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xudoyuan
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May 14, 2026
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