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1. fifo_tb.sv fifo_tb.sv Public template

   - Synchronous FIFO operates under a single clock domain, meaning both read and write actions are triggered by the same clock signal.

   1

2. d_flipflop_sv d_flipflop_sv Public

   The D_ff is a sequential circuit ,the function of d_ff is whatever the input is given to the terminal the output of q is same ,qbar will be constrast.Also i write it in uvm style like testbench,env…

   SystemVerilog 1

3. And-gate- And-gate- Public

   And gate is a basic digital logic gate, if the output is 1 when all inputs are 1, if any one of the inputs or both inputs are 0 the output will become 0. I just write it in both behaviour model, da…

4. And-gate And-gate Public

   And gate is a fundamental digital logic gate, if the output is 1 then input is 1, incase if anyone of the input is 0 the output will become 0. I just write code in dataflow, behavioral model.

   Verilog

5. Halfadder.v Halfadder.v Public

   A Half adder used in binary Arithmetic. It adds two single bit binary numbers and produces sum & carry. The sum output works on XOR operation, carry output works on AND operation i.e, means if two …

   Verilog

6. up_counter-rename-counter up_counter-rename-counter Public

   up_counter-> incrementing, down_counter-> decrementimg

   SystemVerilog